Ultra-low power CMOS circuits
Technology being ever-changing holds large demand for ultra-low power circuits. Transistors operating in the sub-threshold regions have recently showed large potential for ultra-low power purposes. Having a large variety of circuits/techniques available for sub-threshold operation, many were...
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| Other Authors: | |
| Format: | Final Year Project (FYP) |
| Language: | English |
| Published: |
2013
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| Online Access: | http://hdl.handle.net/10356/54467 |
| _version_ | 1811688196819386368 |
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| author | Tan, Jian An. |
| author2 | Lau Kim Teen |
| author_facet | Lau Kim Teen Tan, Jian An. |
| author_sort | Tan, Jian An. |
| collection | NTU |
| description | Technology being ever-changing holds large demand for ultra-low power circuits. Transistors operating in the sub-threshold regions have recently showed large potential for ultra-low power purposes.
Having a large variety of circuits/techniques available for sub-threshold operation, many were examined during the course of the project. However, in order to attain ULP consumption, circuit performance was one of the greatest trade-offs incurred when voltage scaling was performed. Besides, transistor sizing also holds a crucial role during circuit design.
Investigation of ultra-low power design considerations and techniques were performed via simulations in Cadence software utilizing the Global Foundries 65nm process. This in time led to the development of an application that could prove useful in bidirectional counters. |
| first_indexed | 2024-10-01T05:28:22Z |
| format | Final Year Project (FYP) |
| id | ntu-10356/54467 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T05:28:22Z |
| publishDate | 2013 |
| record_format | dspace |
| spelling | ntu-10356/544672023-07-07T16:39:48Z Ultra-low power CMOS circuits Tan, Jian An. Lau Kim Teen School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering Technology being ever-changing holds large demand for ultra-low power circuits. Transistors operating in the sub-threshold regions have recently showed large potential for ultra-low power purposes. Having a large variety of circuits/techniques available for sub-threshold operation, many were examined during the course of the project. However, in order to attain ULP consumption, circuit performance was one of the greatest trade-offs incurred when voltage scaling was performed. Besides, transistor sizing also holds a crucial role during circuit design. Investigation of ultra-low power design considerations and techniques were performed via simulations in Cadence software utilizing the Global Foundries 65nm process. This in time led to the development of an application that could prove useful in bidirectional counters. Bachelor of Engineering 2013-06-20T08:36:53Z 2013-06-20T08:36:53Z 2013 2013 Final Year Project (FYP) http://hdl.handle.net/10356/54467 en Nanyang Technological University 166 p. application/pdf application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering Tan, Jian An. Ultra-low power CMOS circuits |
| title | Ultra-low power CMOS circuits |
| title_full | Ultra-low power CMOS circuits |
| title_fullStr | Ultra-low power CMOS circuits |
| title_full_unstemmed | Ultra-low power CMOS circuits |
| title_short | Ultra-low power CMOS circuits |
| title_sort | ultra low power cmos circuits |
| topic | DRNTU::Engineering::Electrical and electronic engineering |
| url | http://hdl.handle.net/10356/54467 |
| work_keys_str_mv | AT tanjianan ultralowpowercmoscircuits |