Low power CMOS parallel prefix adders
Addition is the basic operation in many modern electronic applications. As the fastest adder, parallel prefix adder is of most interest for many circuit designers. For the past few decades, supply voltage and the size of transistors have been reduced tremendously. With more and...
Main Author: | Yang, Shaochen |
---|---|
Other Authors: | Lau Kim Teen |
Format: | Thesis |
Language: | English |
Published: |
2013
|
Subjects: | |
Online Access: | http://hdl.handle.net/10356/54882 |
Similar Items
-
Design and simulation of CMOS-based imprecise full adders
by: Wu, Chenxi
Published: (2015) -
Data-driven dynamic logic for low power adders and multipliers
by: Mahendiran Navasakthi
Published: (2018) -
An enhanced low-power high-speed adder for error-tolerant application
by: Zhu, Ning, et al.
Published: (2010) -
Design of ultra low power 1-bit full adder cell for logic devices
by: Kumar, Abhishek
Published: (2019) -
Ultra-low power CMOS circuit for IoT
by: Lau, Fong Hou
Published: (2019)