32-bit adders using adiabatic switching for low power IC design
This dissertation describes the implementation of 32-bit adders using different adiabatic logic families. Adiabatic switching is a technique of power reduction where the energy taken from the power supply is recycled or reused. The adder is the most commonly used and critical arithmetic ope...
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| Other Authors: | |
| Format: | Thesis |
| Language: | English |
| Published: |
2013
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| Online Access: | http://hdl.handle.net/10356/54906 |
| _version_ | 1811678326773776384 |
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| author | Joseph, Dhannya Mary |
| author2 | Lau Kim Teen |
| author_facet | Lau Kim Teen Joseph, Dhannya Mary |
| author_sort | Joseph, Dhannya Mary |
| collection | NTU |
| description | This dissertation describes the implementation of 32-bit adders using different
adiabatic logic families. Adiabatic switching is a technique of power reduction where
the energy taken from the power supply is recycled or reused. The adder is the most
commonly used and critical arithmetic operator which determines the throughput of
the processor. It is for this reason that the power reduction is shown in 32-bit adders.
Three adiabatic logic families are used for comparison in this dissertation- Efficient
Charge Recovery Logic (ECRL), Clocked CMOS Adiabatic Logic (CAL) and
Complementary Energy Path Adiabatic Logic (CEPAL). Initially inverter circuits
were implemented using each of these logic styles and compared with vanilla CMOS
in terms of power consumption. Next, I-bit full adder circuits were implemented for
each of the adiabatic logic styles and compared with vanilla CMOS. 32-bit adders
were then implemented and compared to observe the reduction in power
consumption. The adders were also tested to see under what range of voltage and
frequency the operation is consistent. All the circuits were realized using 65nm
CMOS technology using Cadence Virtuoso.
There was a significant reduction in power consumption when adiabatic circuits were
used. ECRL circuit eliminates the need for diodes but the power saving is not
significant compared to the other logic families (44.5% power saving compared to
conventional CMOS). The CEPAL has an edge over the other families because it has
the simplest power clock generator circuitry as only a sinusoidal power clock is
required. However it requires more number of transistors for its implementation. The
power consumption is less than ECRL circuits but more than CAL circuits. When
compared with vanilla CMOS a power saving of 67.8% was observed. The
maximum energy efficiency, 90% saving over conventional CMOS, is observed for
CAL circuits and it can also operate at up to 250MHz at 3V and as low at 1.2V when
operated at 50MHz. The CAL circuit requires an additional square wave clock signal
which acts as an auxiliary clock, thereby increasing the complexity of the power
clock generator. |
| first_indexed | 2024-10-01T02:51:29Z |
| format | Thesis |
| id | ntu-10356/54906 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T02:51:29Z |
| publishDate | 2013 |
| record_format | dspace |
| spelling | ntu-10356/549062023-07-04T15:34:19Z 32-bit adders using adiabatic switching for low power IC design Joseph, Dhannya Mary Lau Kim Teen School of Electrical and Electronic Engineering DRNTU::Engineering This dissertation describes the implementation of 32-bit adders using different adiabatic logic families. Adiabatic switching is a technique of power reduction where the energy taken from the power supply is recycled or reused. The adder is the most commonly used and critical arithmetic operator which determines the throughput of the processor. It is for this reason that the power reduction is shown in 32-bit adders. Three adiabatic logic families are used for comparison in this dissertation- Efficient Charge Recovery Logic (ECRL), Clocked CMOS Adiabatic Logic (CAL) and Complementary Energy Path Adiabatic Logic (CEPAL). Initially inverter circuits were implemented using each of these logic styles and compared with vanilla CMOS in terms of power consumption. Next, I-bit full adder circuits were implemented for each of the adiabatic logic styles and compared with vanilla CMOS. 32-bit adders were then implemented and compared to observe the reduction in power consumption. The adders were also tested to see under what range of voltage and frequency the operation is consistent. All the circuits were realized using 65nm CMOS technology using Cadence Virtuoso. There was a significant reduction in power consumption when adiabatic circuits were used. ECRL circuit eliminates the need for diodes but the power saving is not significant compared to the other logic families (44.5% power saving compared to conventional CMOS). The CEPAL has an edge over the other families because it has the simplest power clock generator circuitry as only a sinusoidal power clock is required. However it requires more number of transistors for its implementation. The power consumption is less than ECRL circuits but more than CAL circuits. When compared with vanilla CMOS a power saving of 67.8% was observed. The maximum energy efficiency, 90% saving over conventional CMOS, is observed for CAL circuits and it can also operate at up to 250MHz at 3V and as low at 1.2V when operated at 50MHz. The CAL circuit requires an additional square wave clock signal which acts as an auxiliary clock, thereby increasing the complexity of the power clock generator. Master of Science (Electronics) 2013-10-24T08:26:33Z 2013-10-24T08:26:33Z 2013 2013 Thesis http://hdl.handle.net/10356/54906 en 110 p. application/pdf |
| spellingShingle | DRNTU::Engineering Joseph, Dhannya Mary 32-bit adders using adiabatic switching for low power IC design |
| title | 32-bit adders using adiabatic switching for low power IC design |
| title_full | 32-bit adders using adiabatic switching for low power IC design |
| title_fullStr | 32-bit adders using adiabatic switching for low power IC design |
| title_full_unstemmed | 32-bit adders using adiabatic switching for low power IC design |
| title_short | 32-bit adders using adiabatic switching for low power IC design |
| title_sort | 32 bit adders using adiabatic switching for low power ic design |
| topic | DRNTU::Engineering |
| url | http://hdl.handle.net/10356/54906 |
| work_keys_str_mv | AT josephdhannyamary 32bitaddersusingadiabaticswitchingforlowpowericdesign |