Efficient FPGA implementation of advanced encryption standard
Nowadays, the security of data is playing an increasingly important role in the data transfer. The encryption algorithm is the core of the data encryption system and change very fast in the decade. At present, AES (Advanced Encryption Standard) algorithm which is also known as Rijndael algorithm is...
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| Other Authors: | |
| Format: | Final Year Project (FYP) |
| Language: | English |
| Published: |
2014
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| Online Access: | http://hdl.handle.net/10356/59200 |
| _version_ | 1811689403793276928 |
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| author | Li, Jiaxiang |
| author2 | Pramod Kumar Meher |
| author_facet | Pramod Kumar Meher Li, Jiaxiang |
| author_sort | Li, Jiaxiang |
| collection | NTU |
| description | Nowadays, the security of data is playing an increasingly important role in the data transfer. The encryption algorithm is the core of the data encryption system and change very fast in the decade. At present, AES (Advanced Encryption Standard) algorithm which is also known as Rijndael algorithm is widely used in the industry.
The encryption system can be implemented in hardware and software. Hardware implementation has advantages on cost and can be optimized in aspect of performance, especially in the situation that the data flow is large. In this project, I will use FPGA to implement AES encryption algorithm.
This report will focus on how to implement the AES by using FPGA in an efficient way, and by using pipelining, parallel processing and pipeline reconfiguration, we can reduce the risk of power analysis attack. The AES algorithm is implemented by Verilog. |
| first_indexed | 2024-10-01T05:47:33Z |
| format | Final Year Project (FYP) |
| id | ntu-10356/59200 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T05:47:33Z |
| publishDate | 2014 |
| record_format | dspace |
| spelling | ntu-10356/592002023-03-03T20:28:32Z Efficient FPGA implementation of advanced encryption standard Li, Jiaxiang Pramod Kumar Meher School of Computer Engineering Centre for High Performance Embedded Systems DRNTU::Engineering::Computer science and engineering Nowadays, the security of data is playing an increasingly important role in the data transfer. The encryption algorithm is the core of the data encryption system and change very fast in the decade. At present, AES (Advanced Encryption Standard) algorithm which is also known as Rijndael algorithm is widely used in the industry. The encryption system can be implemented in hardware and software. Hardware implementation has advantages on cost and can be optimized in aspect of performance, especially in the situation that the data flow is large. In this project, I will use FPGA to implement AES encryption algorithm. This report will focus on how to implement the AES by using FPGA in an efficient way, and by using pipelining, parallel processing and pipeline reconfiguration, we can reduce the risk of power analysis attack. The AES algorithm is implemented by Verilog. Bachelor of Engineering (Computer Engineering) 2014-04-25T04:50:01Z 2014-04-25T04:50:01Z 2014 2014 Final Year Project (FYP) http://hdl.handle.net/10356/59200 en Nanyang Technological University 47 p. application/pdf |
| spellingShingle | DRNTU::Engineering::Computer science and engineering Li, Jiaxiang Efficient FPGA implementation of advanced encryption standard |
| title | Efficient FPGA implementation of advanced encryption standard |
| title_full | Efficient FPGA implementation of advanced encryption standard |
| title_fullStr | Efficient FPGA implementation of advanced encryption standard |
| title_full_unstemmed | Efficient FPGA implementation of advanced encryption standard |
| title_short | Efficient FPGA implementation of advanced encryption standard |
| title_sort | efficient fpga implementation of advanced encryption standard |
| topic | DRNTU::Engineering::Computer science and engineering |
| url | http://hdl.handle.net/10356/59200 |
| work_keys_str_mv | AT lijiaxiang efficientfpgaimplementationofadvancedencryptionstandard |