Asynchronous logic quasi delay insensitive (QDI) static/dynamic/pass logic transistor-level implementation half/full buffer realization approaches for robust VLSI system
This report targeted to explore the characteristics of different types of asynchronous logic quasi-delay-insensitive circuit design. High performance electronic circuit is the main design goal for current technology. However, the performance of traditional synchronous logic circuit is often limit...
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| Other Authors: | |
| Format: | Final Year Project (FYP) |
| Language: | English |
| Published: |
2014
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| Online Access: | http://hdl.handle.net/10356/60438 |
| _version_ | 1824455350253780992 |
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| author | Tsui, Yun Kan |
| author2 | Gwee Bah Hwee |
| author_facet | Gwee Bah Hwee Tsui, Yun Kan |
| author_sort | Tsui, Yun Kan |
| collection | NTU |
| description | This report targeted to explore the characteristics of different types of asynchronous logic
quasi-delay-insensitive circuit design. High performance electronic circuit is the main design
goal for current technology. However, the performance of traditional synchronous logic
circuit is often limited by the global clock signal. Asynchronous logic should be the future
direction of logic design that have the potential to overcome this issue. In this project, five
types of asynchronous design technique, which included Static/Dynamic/Pass Logic
Transistor-level Implementation, Pre-Charged Half-Buffer and Weak-Conditioned Half-
Buffer and four key parameters, which included Delay, Power consumption, Energy
consumption and Number of transistor used were experimented. The results of this project
showed each type of design technique has its unique characteristic. A complete comparison
table is included in the appendix to provide a clear comparison of the results obtained in this
project. |
| first_indexed | 2025-02-19T03:36:48Z |
| format | Final Year Project (FYP) |
| id | ntu-10356/60438 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2025-02-19T03:36:48Z |
| publishDate | 2014 |
| record_format | dspace |
| spelling | ntu-10356/604382023-07-07T17:30:25Z Asynchronous logic quasi delay insensitive (QDI) static/dynamic/pass logic transistor-level implementation half/full buffer realization approaches for robust VLSI system Tsui, Yun Kan Gwee Bah Hwee School of Electrical and Electronic Engineering DRNTU::Engineering This report targeted to explore the characteristics of different types of asynchronous logic quasi-delay-insensitive circuit design. High performance electronic circuit is the main design goal for current technology. However, the performance of traditional synchronous logic circuit is often limited by the global clock signal. Asynchronous logic should be the future direction of logic design that have the potential to overcome this issue. In this project, five types of asynchronous design technique, which included Static/Dynamic/Pass Logic Transistor-level Implementation, Pre-Charged Half-Buffer and Weak-Conditioned Half- Buffer and four key parameters, which included Delay, Power consumption, Energy consumption and Number of transistor used were experimented. The results of this project showed each type of design technique has its unique characteristic. A complete comparison table is included in the appendix to provide a clear comparison of the results obtained in this project. Bachelor of Engineering 2014-05-27T06:02:00Z 2014-05-27T06:02:00Z 2014 2014 Final Year Project (FYP) http://hdl.handle.net/10356/60438 en Nanyang Technological University 106 p. application/pdf |
| spellingShingle | DRNTU::Engineering Tsui, Yun Kan Asynchronous logic quasi delay insensitive (QDI) static/dynamic/pass logic transistor-level implementation half/full buffer realization approaches for robust VLSI system |
| title | Asynchronous logic quasi delay insensitive (QDI) static/dynamic/pass logic transistor-level implementation half/full buffer realization approaches for robust VLSI system |
| title_full | Asynchronous logic quasi delay insensitive (QDI) static/dynamic/pass logic transistor-level implementation half/full buffer realization approaches for robust VLSI system |
| title_fullStr | Asynchronous logic quasi delay insensitive (QDI) static/dynamic/pass logic transistor-level implementation half/full buffer realization approaches for robust VLSI system |
| title_full_unstemmed | Asynchronous logic quasi delay insensitive (QDI) static/dynamic/pass logic transistor-level implementation half/full buffer realization approaches for robust VLSI system |
| title_short | Asynchronous logic quasi delay insensitive (QDI) static/dynamic/pass logic transistor-level implementation half/full buffer realization approaches for robust VLSI system |
| title_sort | asynchronous logic quasi delay insensitive qdi static dynamic pass logic transistor level implementation half full buffer realization approaches for robust vlsi system |
| topic | DRNTU::Engineering |
| url | http://hdl.handle.net/10356/60438 |
| work_keys_str_mv | AT tsuiyunkan asynchronouslogicquasidelayinsensitiveqdistaticdynamicpasslogictransistorlevelimplementationhalffullbufferrealizationapproachesforrobustvlsisystem |