Poly-si nanowire based thin film transistors

This report compiled all the works that had been done by the author during his Final Year Project subject to fulfill the course requirement under School of Electrical and Electronic Engineering (EEE), Nanyang Technological Univeristy. It mainly consists of 1 main project and 2 sub-projects as briefl...

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Main Author: Le, Tien Thanh
Other Authors: Yu Hongyu
Format: Final Year Project (FYP)
Language:English
Published: 2015
Subjects:
Online Access:http://hdl.handle.net/10356/61996
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author Le, Tien Thanh
author2 Yu Hongyu
author_facet Yu Hongyu
Le, Tien Thanh
author_sort Le, Tien Thanh
collection NTU
description This report compiled all the works that had been done by the author during his Final Year Project subject to fulfill the course requirement under School of Electrical and Electronic Engineering (EEE), Nanyang Technological Univeristy. It mainly consists of 1 main project and 2 sub-projects as briefly described below. Main project: Device fabrication and characterization of a polycrystalline silicon (poly- Si) vertical nanowire (VNW) based Thin Film Transistor (TFT). This part of the report demonstrates the fabrication process as well as device characterization of an inverter. With the NMOS to PMOS ratio of 1:1, the inverter exhibits very good performance with high drive current (~100μA/μm), good subthreshold slope (SS ~80-100mV/dec), low drain-induced barrier lowering (DIBL ~20-60mV/V) and high ION/IOFF ratio (~107). Together with good uniformity, this enables the device to be compatible for system on panel driving circuitry fabrication. CMOS compatible VNW devices could also realize 3D integration that will further improve device packing density and at the same time reduce power consumption.
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spelling ntu-10356/619962023-07-07T15:53:14Z Poly-si nanowire based thin film transistors Le, Tien Thanh Yu Hongyu School of Electrical and Electronic Engineering A*STAR Institute of Microelectronics DRNTU::Engineering::Electrical and electronic engineering::Nanoelectronics This report compiled all the works that had been done by the author during his Final Year Project subject to fulfill the course requirement under School of Electrical and Electronic Engineering (EEE), Nanyang Technological Univeristy. It mainly consists of 1 main project and 2 sub-projects as briefly described below. Main project: Device fabrication and characterization of a polycrystalline silicon (poly- Si) vertical nanowire (VNW) based Thin Film Transistor (TFT). This part of the report demonstrates the fabrication process as well as device characterization of an inverter. With the NMOS to PMOS ratio of 1:1, the inverter exhibits very good performance with high drive current (~100μA/μm), good subthreshold slope (SS ~80-100mV/dec), low drain-induced barrier lowering (DIBL ~20-60mV/V) and high ION/IOFF ratio (~107). Together with good uniformity, this enables the device to be compatible for system on panel driving circuitry fabrication. CMOS compatible VNW devices could also realize 3D integration that will further improve device packing density and at the same time reduce power consumption. Bachelor of Engineering 2015-01-05T02:01:40Z 2015-01-05T02:01:40Z 2010 2010 Final Year Project (FYP) http://hdl.handle.net/10356/61996 en Nanyang Technological University 64 p. application/pdf
spellingShingle DRNTU::Engineering::Electrical and electronic engineering::Nanoelectronics
Le, Tien Thanh
Poly-si nanowire based thin film transistors
title Poly-si nanowire based thin film transistors
title_full Poly-si nanowire based thin film transistors
title_fullStr Poly-si nanowire based thin film transistors
title_full_unstemmed Poly-si nanowire based thin film transistors
title_short Poly-si nanowire based thin film transistors
title_sort poly si nanowire based thin film transistors
topic DRNTU::Engineering::Electrical and electronic engineering::Nanoelectronics
url http://hdl.handle.net/10356/61996
work_keys_str_mv AT letienthanh polysinanowirebasedthinfilmtransistors