Automation and optimization of a CUDA to FPGA high level synthesis tool
In this report, I will show that the current CUDA-to-FPGA (FCUDA) flow has been tested with a good set of CUDA kernels collecting from NVIDIA CUDA SDK, Parboil Benchmark suite, and Rodinia Benchmark suite. The testing flows will be discussed thoroughly along with many optimization decisions. It also...
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| Format: | Final Year Project (FYP) |
| Language: | English |
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2015
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| Online Access: | http://hdl.handle.net/10356/63163 |
| _version_ | 1811681218871164928 |
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| author | Tan, Nguyen Quoc Duy |
| author2 | Kyle Rupnow |
| author_facet | Kyle Rupnow Tan, Nguyen Quoc Duy |
| author_sort | Tan, Nguyen Quoc Duy |
| collection | NTU |
| description | In this report, I will show that the current CUDA-to-FPGA (FCUDA) flow has been tested with a good set of CUDA kernels collecting from NVIDIA CUDA SDK, Parboil Benchmark suite, and Rodinia Benchmark suite. The testing flows will be discussed thoroughly along with many optimization decisions. It also includes some guidelines of using FCUDA to translate a CUDA kernel to a sequential C code by inserting correct FCUDA-specific pragmas in the CUDA kernel code. The report will also demonstrate a simple flow of integrating FCUDA onto a real System-on-a-Chip (SoC) platform, for example, the Zynq 7000 Zedboard from Xilinx. This achievement is significant as it brings the project to a higher level: hardware platform integration. |
| first_indexed | 2024-10-01T03:37:27Z |
| format | Final Year Project (FYP) |
| id | ntu-10356/63163 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T03:37:27Z |
| publishDate | 2015 |
| record_format | dspace |
| spelling | ntu-10356/631632023-03-03T20:27:25Z Automation and optimization of a CUDA to FPGA high level synthesis tool Tan, Nguyen Quoc Duy Kyle Rupnow School of Computer Engineering Centre for High Performance Embedded Systems DRNTU::Engineering::Computer science and engineering::Hardware In this report, I will show that the current CUDA-to-FPGA (FCUDA) flow has been tested with a good set of CUDA kernels collecting from NVIDIA CUDA SDK, Parboil Benchmark suite, and Rodinia Benchmark suite. The testing flows will be discussed thoroughly along with many optimization decisions. It also includes some guidelines of using FCUDA to translate a CUDA kernel to a sequential C code by inserting correct FCUDA-specific pragmas in the CUDA kernel code. The report will also demonstrate a simple flow of integrating FCUDA onto a real System-on-a-Chip (SoC) platform, for example, the Zynq 7000 Zedboard from Xilinx. This achievement is significant as it brings the project to a higher level: hardware platform integration. Bachelor of Engineering (Computer Engineering) 2015-05-08T02:41:39Z 2015-05-08T02:41:39Z 2015 2015 Final Year Project (FYP) http://hdl.handle.net/10356/63163 en Nanyang Technological University 72 p. application/pdf |
| spellingShingle | DRNTU::Engineering::Computer science and engineering::Hardware Tan, Nguyen Quoc Duy Automation and optimization of a CUDA to FPGA high level synthesis tool |
| title | Automation and optimization of a CUDA to FPGA high level synthesis tool |
| title_full | Automation and optimization of a CUDA to FPGA high level synthesis tool |
| title_fullStr | Automation and optimization of a CUDA to FPGA high level synthesis tool |
| title_full_unstemmed | Automation and optimization of a CUDA to FPGA high level synthesis tool |
| title_short | Automation and optimization of a CUDA to FPGA high level synthesis tool |
| title_sort | automation and optimization of a cuda to fpga high level synthesis tool |
| topic | DRNTU::Engineering::Computer science and engineering::Hardware |
| url | http://hdl.handle.net/10356/63163 |
| work_keys_str_mv | AT tannguyenquocduy automationandoptimizationofacudatofpgahighlevelsynthesistool |