| Summary: | In these years, logic circuits intend to develop towards low energy consumption.
Therefore, adiabatic logic was brought up to tackle the problem. In this dissertation,
adiabatic theory was introduced and adiabatic logic's, including ECRL, CEPAL and
CAL were presented and simulated in Cadence. Power Consumption were compared
in various periods. Then five 1-bit adders, conventional CMOS, dynamic, CEPAL,
ECRL and CAL were simulated. Power consumption in different supply voltages
and periods were compared. Then, 8-bit adders using adiabatic logic's were designed
and simulated. At last, conclusions were drawn from the simulation results.
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