Low power CMOS and adiabatic arithmetic units
In these years, logic circuits intend to develop towards low energy consumption. Therefore, adiabatic logic was brought up to tackle the problem. In this dissertation, adiabatic theory was introduced and adiabatic logic's, including ECRL, CEPAL and CAL were presented and simulated in C...
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| Other Authors: | |
| Format: | Thesis |
| Language: | English |
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2015
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| Online Access: | http://hdl.handle.net/10356/64772 |
| _version_ | 1826127814506577920 |
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| author | Meng, Xing |
| author2 | Lau Kim Teen |
| author_facet | Lau Kim Teen Meng, Xing |
| author_sort | Meng, Xing |
| collection | NTU |
| description | In these years, logic circuits intend to develop towards low energy consumption.
Therefore, adiabatic logic was brought up to tackle the problem. In this dissertation,
adiabatic theory was introduced and adiabatic logic's, including ECRL, CEPAL and
CAL were presented and simulated in Cadence. Power Consumption were compared
in various periods. Then five 1-bit adders, conventional CMOS, dynamic, CEPAL,
ECRL and CAL were simulated. Power consumption in different supply voltages
and periods were compared. Then, 8-bit adders using adiabatic logic's were designed
and simulated. At last, conclusions were drawn from the simulation results. |
| first_indexed | 2024-10-01T07:14:38Z |
| format | Thesis |
| id | ntu-10356/64772 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T07:14:38Z |
| publishDate | 2015 |
| record_format | dspace |
| spelling | ntu-10356/647722023-07-04T15:24:20Z Low power CMOS and adiabatic arithmetic units Meng, Xing Lau Kim Teen School of Electrical and Electronic Engineering DRNTU::Engineering In these years, logic circuits intend to develop towards low energy consumption. Therefore, adiabatic logic was brought up to tackle the problem. In this dissertation, adiabatic theory was introduced and adiabatic logic's, including ECRL, CEPAL and CAL were presented and simulated in Cadence. Power Consumption were compared in various periods. Then five 1-bit adders, conventional CMOS, dynamic, CEPAL, ECRL and CAL were simulated. Power consumption in different supply voltages and periods were compared. Then, 8-bit adders using adiabatic logic's were designed and simulated. At last, conclusions were drawn from the simulation results. Master of Science (Electronics) 2015-06-04T02:00:52Z 2015-06-04T02:00:52Z 2014 2014 Thesis http://hdl.handle.net/10356/64772 en 71 p. application/pdf |
| spellingShingle | DRNTU::Engineering Meng, Xing Low power CMOS and adiabatic arithmetic units |
| title | Low power CMOS and adiabatic arithmetic units |
| title_full | Low power CMOS and adiabatic arithmetic units |
| title_fullStr | Low power CMOS and adiabatic arithmetic units |
| title_full_unstemmed | Low power CMOS and adiabatic arithmetic units |
| title_short | Low power CMOS and adiabatic arithmetic units |
| title_sort | low power cmos and adiabatic arithmetic units |
| topic | DRNTU::Engineering |
| url | http://hdl.handle.net/10356/64772 |
| work_keys_str_mv | AT mengxing lowpowercmosandadiabaticarithmeticunits |