Reconfigurable baseband design for multi-mode, multi-rate wireless communication
Low-density parity-check code (LDPC code) is a kind of linear block error-correcting code defined by sparse matrices. When the code is long enough, the performance of LPDC codes is even better than Turbo codes, which has made it a strong competitor of the fourth-generation communication systems (...
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| Muut tekijät: | |
| Aineistotyyppi: | Opinnäyte |
| Kieli: | English |
| Julkaistu: |
2015
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| Aiheet: | |
| Linkit: | http://hdl.handle.net/10356/65067 |
| _version_ | 1826111098227523584 |
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| author | Zhang, Yun |
| author2 | Goh Wang Ling |
| author_facet | Goh Wang Ling Zhang, Yun |
| author_sort | Zhang, Yun |
| collection | NTU |
| description | Low-density parity-check code (LDPC code) is a kind of linear block
error-correcting code defined by sparse matrices. When the code is long enough, the
performance of LPDC codes is even better than Turbo codes, which has made it a
strong competitor of the fourth-generation communication systems ( 4G). It has been
adopted by many advanced standards, such as digital video broadcasting (DVB-S2).
In recent years, LDPC codes have become one of the hottest topics in the field of
error-correcting codes.
This dissertation shows studies on the theory of encoding and decoding
algorithms of LDPC codes and its hardware design and implementation. The main
decoding algorithms introduced in this dissertation are Bit-Flipping algorithm,
Sum-Product algorithm and Min-Sum algorithm. These algorithms decide the
architecture and performance of the decoder.
There are mainly three architectures. They are fully parallel, row-parallel and
block-parallel architectures. Current research work on LDPC decoders mainly
focuses on four aspects: structured LDPC codes, error floor reduction, reconfigurable
decoder design and routing congestion reduction. According to the Tanner graph, the
processors of the rows and columns are connected directly in a fully parallel decoder,
which could provide high through puts. However, implementing the decoder is quite
challenging due to the high interconnect complexity in terms of row and column
processors. To solve this problem, a method called "Split-Row" is proposed, which
significantly reduce processor logical complexity, local and global interconnections.
Finally, a fully parallel decoder is implemented by using Verilog HDL, according to
corresponding structures. |
| first_indexed | 2024-10-01T02:45:03Z |
| format | Thesis |
| id | ntu-10356/65067 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T02:45:03Z |
| publishDate | 2015 |
| record_format | dspace |
| spelling | ntu-10356/650672023-07-04T15:47:03Z Reconfigurable baseband design for multi-mode, multi-rate wireless communication Zhang, Yun Goh Wang Ling School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering Low-density parity-check code (LDPC code) is a kind of linear block error-correcting code defined by sparse matrices. When the code is long enough, the performance of LPDC codes is even better than Turbo codes, which has made it a strong competitor of the fourth-generation communication systems ( 4G). It has been adopted by many advanced standards, such as digital video broadcasting (DVB-S2). In recent years, LDPC codes have become one of the hottest topics in the field of error-correcting codes. This dissertation shows studies on the theory of encoding and decoding algorithms of LDPC codes and its hardware design and implementation. The main decoding algorithms introduced in this dissertation are Bit-Flipping algorithm, Sum-Product algorithm and Min-Sum algorithm. These algorithms decide the architecture and performance of the decoder. There are mainly three architectures. They are fully parallel, row-parallel and block-parallel architectures. Current research work on LDPC decoders mainly focuses on four aspects: structured LDPC codes, error floor reduction, reconfigurable decoder design and routing congestion reduction. According to the Tanner graph, the processors of the rows and columns are connected directly in a fully parallel decoder, which could provide high through puts. However, implementing the decoder is quite challenging due to the high interconnect complexity in terms of row and column processors. To solve this problem, a method called "Split-Row" is proposed, which significantly reduce processor logical complexity, local and global interconnections. Finally, a fully parallel decoder is implemented by using Verilog HDL, according to corresponding structures. Master of Science 2015-06-12T08:54:30Z 2015-06-12T08:54:30Z 2014 2014 Thesis http://hdl.handle.net/10356/65067 en 74 p. application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering Zhang, Yun Reconfigurable baseband design for multi-mode, multi-rate wireless communication |
| title | Reconfigurable baseband design for multi-mode, multi-rate wireless communication |
| title_full | Reconfigurable baseband design for multi-mode, multi-rate wireless communication |
| title_fullStr | Reconfigurable baseband design for multi-mode, multi-rate wireless communication |
| title_full_unstemmed | Reconfigurable baseband design for multi-mode, multi-rate wireless communication |
| title_short | Reconfigurable baseband design for multi-mode, multi-rate wireless communication |
| title_sort | reconfigurable baseband design for multi mode multi rate wireless communication |
| topic | DRNTU::Engineering::Electrical and electronic engineering |
| url | http://hdl.handle.net/10356/65067 |
| work_keys_str_mv | AT zhangyun reconfigurablebasebanddesignformultimodemultiratewirelesscommunication |