Design analysis of data links in 2.5 dics
As the trend of device integration moves from VLSI to ULSI, number of problems have arisen for 3 dimensional integration of ICs with TSV technology. The increasing complexity and number of components on the substrate is expected to rise faster before Nano-technology takes over. 2.5DICs are a viable...
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Thesis |
| Language: | English |
| Published: |
2015
|
| Subjects: | |
| Online Access: | http://hdl.handle.net/10356/65074 |
| _version_ | 1824454537480503296 |
|---|---|
| author | Visamangalam Thattai Lakshminarayanan |
| author2 | Kim Tae Hyoung |
| author_facet | Kim Tae Hyoung Visamangalam Thattai Lakshminarayanan |
| author_sort | Visamangalam Thattai Lakshminarayanan |
| collection | NTU |
| description | As the trend of device integration moves from VLSI to ULSI, number of problems have arisen for 3 dimensional integration of ICs with TSV technology. The increasing complexity and number of components on the substrate is expected to rise
faster before Nano-technology takes over. 2.5DICs are a viable market alternative till the 3DIC processes and methods mature. 3DICs require multiple ICs to be placed on top of each other and interconnected by TSVs, which cause power delivery and thermal delivery problems. Individual known good dies connected in 3D fashion gives poor yields and get discarded if the integrated IC fails. 2.5DICs allow interconnection of multiple chips on the same Si substrate placed side to side with interconnections made using Si interposer with multiple metal layers. In this project, non conventional transmission line structures are proposed to improve the layout density of wide 10 high speed data links. The configurations are
modelled and characterized using full wave 3D Electromagnetic field simulator. Results are validated based upon eye diagrams and loss parameters. A Current mode
driver circuit is designed and simulated using STM 65nm technology node. |
| first_indexed | 2025-02-19T03:23:53Z |
| format | Thesis |
| id | ntu-10356/65074 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2025-02-19T03:23:53Z |
| publishDate | 2015 |
| record_format | dspace |
| spelling | ntu-10356/650742023-07-04T15:24:48Z Design analysis of data links in 2.5 dics Visamangalam Thattai Lakshminarayanan Kim Tae Hyoung School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering As the trend of device integration moves from VLSI to ULSI, number of problems have arisen for 3 dimensional integration of ICs with TSV technology. The increasing complexity and number of components on the substrate is expected to rise faster before Nano-technology takes over. 2.5DICs are a viable market alternative till the 3DIC processes and methods mature. 3DICs require multiple ICs to be placed on top of each other and interconnected by TSVs, which cause power delivery and thermal delivery problems. Individual known good dies connected in 3D fashion gives poor yields and get discarded if the integrated IC fails. 2.5DICs allow interconnection of multiple chips on the same Si substrate placed side to side with interconnections made using Si interposer with multiple metal layers. In this project, non conventional transmission line structures are proposed to improve the layout density of wide 10 high speed data links. The configurations are modelled and characterized using full wave 3D Electromagnetic field simulator. Results are validated based upon eye diagrams and loss parameters. A Current mode driver circuit is designed and simulated using STM 65nm technology node. Master of Science (Electronics) 2015-06-12T10:38:40Z 2015-06-12T10:38:40Z 2014 2014 Thesis http://hdl.handle.net/10356/65074 en 67 p. application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering Visamangalam Thattai Lakshminarayanan Design analysis of data links in 2.5 dics |
| title | Design analysis of data links in 2.5 dics |
| title_full | Design analysis of data links in 2.5 dics |
| title_fullStr | Design analysis of data links in 2.5 dics |
| title_full_unstemmed | Design analysis of data links in 2.5 dics |
| title_short | Design analysis of data links in 2.5 dics |
| title_sort | design analysis of data links in 2 5 dics |
| topic | DRNTU::Engineering::Electrical and electronic engineering |
| url | http://hdl.handle.net/10356/65074 |
| work_keys_str_mv | AT visamangalamthattailakshminarayanan designanalysisofdatalinksin25dics |