Performance analysis and comparison of low power dynamic and differential CMOS logic adder circuits
Speed and density IC devices have seen exponential growth in the past few decades. Especially in energy constrained devices like laptops, mobiles and other portable devices improving the battery lifetime is a major challenge faced. By designing low power IC components, we can improve the ov...
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| Other Authors: | |
| Format: | Thesis |
| Language: | English |
| Published: |
2015
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| Online Access: | http://hdl.handle.net/10356/65095 |
| _version_ | 1811684978224791552 |
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| author | Prasanna Dhayalan |
| author2 | Lau Kim Teen |
| author_facet | Lau Kim Teen Prasanna Dhayalan |
| author_sort | Prasanna Dhayalan |
| collection | NTU |
| description | Speed and density IC devices have seen exponential growth in the past few decades.
Especially in energy constrained devices like laptops, mobiles and other portable devices
improving the battery lifetime is a major challenge faced. By designing low power IC
components, we can improve the overall battery life. Adder circuit is the critical
component in any processor. The performance of the whole system depends upon Adder
for a great extent. Thus, in order to reduce the power consumption of a Processor, it is
necessary to design low power adder circuits. Several logic styles are available to design
low power adder circuits. Dynamic and differential logic adders are significant because
of their faster response and low power consumption.
In my project, emphasis has been given on low power Dynamic and differential logic
adders. They show better characteristics in terms of power consumption and response
time. Several dynamic and differential logic styles are taken into study. Performance
parameters: power consumption and delay time are measured and taken for my study.
Dynamic and differential logic devices are compared with static CMOS, Pass transistor
and hybrid CMOS logic adders and Data driven dynamic adder.
All the simulations are done in Cadence environment using CSM 65nm CMOS
technology. |
| first_indexed | 2024-10-01T04:37:13Z |
| format | Thesis |
| id | ntu-10356/65095 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T04:37:13Z |
| publishDate | 2015 |
| record_format | dspace |
| spelling | ntu-10356/650952023-07-04T15:24:14Z Performance analysis and comparison of low power dynamic and differential CMOS logic adder circuits Prasanna Dhayalan Lau Kim Teen School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits Speed and density IC devices have seen exponential growth in the past few decades. Especially in energy constrained devices like laptops, mobiles and other portable devices improving the battery lifetime is a major challenge faced. By designing low power IC components, we can improve the overall battery life. Adder circuit is the critical component in any processor. The performance of the whole system depends upon Adder for a great extent. Thus, in order to reduce the power consumption of a Processor, it is necessary to design low power adder circuits. Several logic styles are available to design low power adder circuits. Dynamic and differential logic adders are significant because of their faster response and low power consumption. In my project, emphasis has been given on low power Dynamic and differential logic adders. They show better characteristics in terms of power consumption and response time. Several dynamic and differential logic styles are taken into study. Performance parameters: power consumption and delay time are measured and taken for my study. Dynamic and differential logic devices are compared with static CMOS, Pass transistor and hybrid CMOS logic adders and Data driven dynamic adder. All the simulations are done in Cadence environment using CSM 65nm CMOS technology. Master of Science (Electronics) 2015-06-15T01:45:25Z 2015-06-15T01:45:25Z 2014 2014 Thesis http://hdl.handle.net/10356/65095 en 91 p. application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits Prasanna Dhayalan Performance analysis and comparison of low power dynamic and differential CMOS logic adder circuits |
| title | Performance analysis and comparison of low power dynamic and differential CMOS logic adder circuits |
| title_full | Performance analysis and comparison of low power dynamic and differential CMOS logic adder circuits |
| title_fullStr | Performance analysis and comparison of low power dynamic and differential CMOS logic adder circuits |
| title_full_unstemmed | Performance analysis and comparison of low power dynamic and differential CMOS logic adder circuits |
| title_short | Performance analysis and comparison of low power dynamic and differential CMOS logic adder circuits |
| title_sort | performance analysis and comparison of low power dynamic and differential cmos logic adder circuits |
| topic | DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits |
| url | http://hdl.handle.net/10356/65095 |
| work_keys_str_mv | AT prasannadhayalan performanceanalysisandcomparisonoflowpowerdynamicanddifferentialcmoslogicaddercircuits |