Design methodologies for robust and low-overhead asynchronous quasi-delay-insensitive digital systems
In the past decades of electronic circuit designs, the synchronous-logic (sync) is the main de-facto design approach for digital systems. This is largely due to its synchronization to a global clock signal (or its variants thereof) which simplifies the data transfer. Nevertheless, designing digital...
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| Format: | Thesis |
| Language: | English |
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2015
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| Online Access: | https://hdl.handle.net/10356/65411 |