Hardware development of three-phase high efficient multilevel converter with reduced clamping components
Multilevel inverters are known to be very essential owing to its vast number of utilizations. There are a variety of fields in which they are being used. Multilevel inverters have taken a common place in many applications and products. They are attractive because they allow for a high number of volt...
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| Format: | Final Year Project (FYP) |
| Language: | English |
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2016
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| Online Access: | http://hdl.handle.net/10356/68252 |
| _version_ | 1826117900318015488 |
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| author | Mohamed Ismail |
| author2 | Ali Iftekhar Maswood |
| author_facet | Ali Iftekhar Maswood Mohamed Ismail |
| author_sort | Mohamed Ismail |
| collection | NTU |
| description | Multilevel inverters are known to be very essential owing to its vast number of utilizations. There are a variety of fields in which they are being used. Multilevel inverters have taken a common place in many applications and products. They are attractive because they allow for a high number of voltage outputs to be synthesized. This grants a good efficiency of power conversion. There are different types of topologies which can be used in the design of inverters. The cost of the inverter varies according to topologies as different topologies use different components. As the number of levels increase in an inverter, the cost will increase as the number of components increases. This report will focus on reducing the cost of a three-phase multilevel converter by combining different topologies to reduce clamping components. The inverter uses a combination of Neutral-Point Clamped and Flying Capacitor topologies to achieve the reduction in cost while achieving good performances. The hardware prototype of the hybrid inverter is developed and then tested for its efficiency. The supplementary level shifter circuits, analogue circuits and gate driver circuits are also developed to power the multilevel inverter. |
| first_indexed | 2024-10-01T04:34:55Z |
| format | Final Year Project (FYP) |
| id | ntu-10356/68252 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T04:34:55Z |
| publishDate | 2016 |
| record_format | dspace |
| spelling | ntu-10356/682522023-07-07T15:58:58Z Hardware development of three-phase high efficient multilevel converter with reduced clamping components Mohamed Ismail Ali Iftekhar Maswood School of Electrical and Electronic Engineering DRNTU::Engineering Multilevel inverters are known to be very essential owing to its vast number of utilizations. There are a variety of fields in which they are being used. Multilevel inverters have taken a common place in many applications and products. They are attractive because they allow for a high number of voltage outputs to be synthesized. This grants a good efficiency of power conversion. There are different types of topologies which can be used in the design of inverters. The cost of the inverter varies according to topologies as different topologies use different components. As the number of levels increase in an inverter, the cost will increase as the number of components increases. This report will focus on reducing the cost of a three-phase multilevel converter by combining different topologies to reduce clamping components. The inverter uses a combination of Neutral-Point Clamped and Flying Capacitor topologies to achieve the reduction in cost while achieving good performances. The hardware prototype of the hybrid inverter is developed and then tested for its efficiency. The supplementary level shifter circuits, analogue circuits and gate driver circuits are also developed to power the multilevel inverter. Bachelor of Engineering 2016-05-25T04:11:14Z 2016-05-25T04:11:14Z 2016 Final Year Project (FYP) http://hdl.handle.net/10356/68252 en Nanyang Technological University 71 p. application/pdf |
| spellingShingle | DRNTU::Engineering Mohamed Ismail Hardware development of three-phase high efficient multilevel converter with reduced clamping components |
| title | Hardware development of three-phase high efficient multilevel converter with reduced clamping components |
| title_full | Hardware development of three-phase high efficient multilevel converter with reduced clamping components |
| title_fullStr | Hardware development of three-phase high efficient multilevel converter with reduced clamping components |
| title_full_unstemmed | Hardware development of three-phase high efficient multilevel converter with reduced clamping components |
| title_short | Hardware development of three-phase high efficient multilevel converter with reduced clamping components |
| title_sort | hardware development of three phase high efficient multilevel converter with reduced clamping components |
| topic | DRNTU::Engineering |
| url | http://hdl.handle.net/10356/68252 |
| work_keys_str_mv | AT mohamedismail hardwaredevelopmentofthreephasehighefficientmultilevelconverterwithreducedclampingcomponents |