16-bit low power multiplier design
Binary multipliers have been commonly used in many arithmetic circuits such that these multipliers are also mainly made up of half and full adders. Adders in the multiplier help to sum up the partial products and the carry bits in different levels depending on the bit size of the multiplier. In orde...
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| Other Authors: | |
| Format: | Final Year Project (FYP) |
| Language: | English |
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2016
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| Online Access: | http://hdl.handle.net/10356/68837 |
| _version_ | 1826120248082825216 |
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| author | Liew Tien Hong |
| author2 | Gwee Bah Hwee |
| author_facet | Gwee Bah Hwee Liew Tien Hong |
| author_sort | Liew Tien Hong |
| collection | NTU |
| description | Binary multipliers have been commonly used in many arithmetic circuits such that these multipliers are also mainly made up of half and full adders. Adders in the multiplier help to sum up the partial products and the carry bits in different levels depending on the bit size of the multiplier. In order to minimize delay and power dissipation, Wallace Tree Algorithm (WTA) has been proposed to perform the partial product additions. For further improvement, Carry Lookahead Adder has been proposed for the final addition of the partial product in the final level. |
| first_indexed | 2024-10-01T05:13:06Z |
| format | Final Year Project (FYP) |
| id | ntu-10356/68837 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T05:13:06Z |
| publishDate | 2016 |
| record_format | dspace |
| spelling | ntu-10356/688372023-07-07T17:22:03Z 16-bit low power multiplier design Liew Tien Hong Gwee Bah Hwee School of Electrical and Electronic Engineering DRNTU::Engineering Binary multipliers have been commonly used in many arithmetic circuits such that these multipliers are also mainly made up of half and full adders. Adders in the multiplier help to sum up the partial products and the carry bits in different levels depending on the bit size of the multiplier. In order to minimize delay and power dissipation, Wallace Tree Algorithm (WTA) has been proposed to perform the partial product additions. For further improvement, Carry Lookahead Adder has been proposed for the final addition of the partial product in the final level. Bachelor of Engineering 2016-06-09T02:56:41Z 2016-06-09T02:56:41Z 2016 Final Year Project (FYP) http://hdl.handle.net/10356/68837 en Nanyang Technological University 37 p. application/pdf application/msword |
| spellingShingle | DRNTU::Engineering Liew Tien Hong 16-bit low power multiplier design |
| title | 16-bit low power multiplier design |
| title_full | 16-bit low power multiplier design |
| title_fullStr | 16-bit low power multiplier design |
| title_full_unstemmed | 16-bit low power multiplier design |
| title_short | 16-bit low power multiplier design |
| title_sort | 16 bit low power multiplier design |
| topic | DRNTU::Engineering |
| url | http://hdl.handle.net/10356/68837 |
| work_keys_str_mv | AT liewtienhong 16bitlowpowermultiplierdesign |