Improving the productivity of high-level synthesis by advancing reuseability and verifiability
As the complexity of applications continues to grow to meet user demands, the complexity of hardware platforms continues to grow correspondingly. Thus, the hardware design flow is a critical methodology to handle continued growth in design complexity. Whether targeting application-specific integr...
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| Format: | Thesis |
| Language: | English |
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2017
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| Online Access: | http://hdl.handle.net/10356/69552 |