Developing secure, ultra-low power RISC processor
General purpose Reduced Instruction Set Computing (RISC) processors are widely used while software applications are interacting with the Operating System (OS) to handle jobs, the OS communicate with the processor to complete the jobs with the help of accelerators. The goal of this project is to impr...
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| Other Authors: | |
| Format: | Final Year Project (FYP) |
| Language: | English |
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2017
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| Online Access: | http://hdl.handle.net/10356/70190 |
| _version_ | 1826117323213242368 |
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| author | Lim, Jun Hao |
| author2 | Anupam Chattopadhyay |
| author_facet | Anupam Chattopadhyay Lim, Jun Hao |
| author_sort | Lim, Jun Hao |
| collection | NTU |
| description | General purpose Reduced Instruction Set Computing (RISC) processors are widely used while software applications are interacting with the Operating System (OS) to handle jobs, the OS communicate with the processor to complete the jobs with the help of accelerators. The goal of this project is to improve the area and speed of the processor while keeping the power usage to the minimum without compromising the security portion.
The design of the processor and programming language will be based on an available open source RISC processor called RISC V, followed by an open source Hardware Description Language (HDL) named Chisel.
By using HDL, the design of the processor will be explored at different levels to meet the goals as mentioned previously. For example, power consumption techniques like clock gating or and operand isolation will be introduced to minimize the power consumption and error correcting codes will be examined to tighten security.
The final design will be synthesized into Zed Board Zynq 7000; a System on Chip development board for accurate benchmarking. |
| first_indexed | 2024-10-01T04:25:44Z |
| format | Final Year Project (FYP) |
| id | ntu-10356/70190 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T04:25:44Z |
| publishDate | 2017 |
| record_format | dspace |
| spelling | ntu-10356/701902023-03-03T20:48:15Z Developing secure, ultra-low power RISC processor Lim, Jun Hao Anupam Chattopadhyay School of Computer Science and Engineering DRNTU::Engineering::Computer science and engineering General purpose Reduced Instruction Set Computing (RISC) processors are widely used while software applications are interacting with the Operating System (OS) to handle jobs, the OS communicate with the processor to complete the jobs with the help of accelerators. The goal of this project is to improve the area and speed of the processor while keeping the power usage to the minimum without compromising the security portion. The design of the processor and programming language will be based on an available open source RISC processor called RISC V, followed by an open source Hardware Description Language (HDL) named Chisel. By using HDL, the design of the processor will be explored at different levels to meet the goals as mentioned previously. For example, power consumption techniques like clock gating or and operand isolation will be introduced to minimize the power consumption and error correcting codes will be examined to tighten security. The final design will be synthesized into Zed Board Zynq 7000; a System on Chip development board for accurate benchmarking. Bachelor of Engineering (Computer Engineering) 2017-04-15T04:53:05Z 2017 Final Year Project (FYP) http://hdl.handle.net/10356/70190 en Nanyang Technological University 63 p. application/pdf |
| spellingShingle | DRNTU::Engineering::Computer science and engineering Lim, Jun Hao Developing secure, ultra-low power RISC processor |
| title | Developing secure, ultra-low power RISC processor |
| title_full | Developing secure, ultra-low power RISC processor |
| title_fullStr | Developing secure, ultra-low power RISC processor |
| title_full_unstemmed | Developing secure, ultra-low power RISC processor |
| title_short | Developing secure, ultra-low power RISC processor |
| title_sort | developing secure ultra low power risc processor |
| topic | DRNTU::Engineering::Computer science and engineering |
| url | http://hdl.handle.net/10356/70190 |
| work_keys_str_mv | AT limjunhao developingsecureultralowpowerriscprocessor |