Low power clock generators with digital calibration for sustainable building applications
The growth of human population on Earth has increased the awareness on the need for energy saving. The concept of smart building and life are proposed to connect all household appliances up to clouds to allow users to control these appliances with energy distribution in a smarter manner. With th...
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Thesis-Doctor of Philosophy |
| Language: | English |
| Published: |
Nanyang Technological University
2017
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| Subjects: | |
| Online Access: | http://hdl.handle.net/10356/70695 |
| _version_ | 1811683734616801280 |
|---|---|
| author | Wang, Jiacheng |
| author2 | Goh Wang Ling |
| author_facet | Goh Wang Ling Wang, Jiacheng |
| author_sort | Wang, Jiacheng |
| collection | NTU |
| description | The growth of human population on Earth has increased the awareness
on the need for energy saving. The concept of smart building and life are
proposed to connect all household appliances up to clouds to allow users to
control these appliances with energy distribution in a smarter manner. With
the expansion of mobile device usage and internet cloud applications, we are
already moving to the big-data age. At the same time, the rapid developing
digital signal processing technique requires the stable clock frequency due
to different building environments, such as wide temperature range, variable
supply voltage, sunshine time, humidity and so on.
This thesis proposes two relaxation oscillator designs and an all-digital
phase locked-loop (ADPLL) design as stable clock frequency generators for
the sustainable building applications.
The first proposed design presents a novel on-chip RC relaxation oscillator
with split-capacitor integrator compensation loop technique to achieve a
stable output frequency with environment temperature and supply voltage
variations. It can provide a stable frequency signal at 13.5 MHz. Measurements
results show that the output frequency has ±0.5% and ±0.5%/V
variation with temperature range of −30◦C to 120◦C and power supply range
of 1.5 − 2.1 V. Moreover, the power consumption of the design yields only
48.8 µW.
The second design is also a relaxation oscillator with digital compensation
technique to achieve a stable output frequency with environment temperature
and supply voltage variations. The digital compensation scheme can
avoid the power hungry analog op-amp integrator feedback loop. The digital
method not only save more power in the long run, but is easier when comes to CMOS process scaling. Furthermore, an on-chip reference pulse generator
is adopted for the compensation. The digital feedback loop tunes loop delay
to adjust the output frequency. The test chips were fabricated in a 0.18-
µm standard CMOS process. Effects of this digital compensation method
has been verified to maintain frequency stability of the relaxation oscillator.
The output frequency is stable at 12.77 MHz at 0.9-V power supply voltage.
Measurement results showed that the output frequency has only 31ppm/◦C
variation with temperature range of -30 to 120◦C after compensation. The
frequency variation over the supply voltage is ±0.5%/V. Compared to other
state-of-the-art designs, our design achieves better figure of merit (FoM) and
has the smallest temperature coefficient. The total power consumption is
56.2 µW when all circuits are enabled. For long term operation, the power
consumption can be scaled to only 12.8 µW in the main oscillator.
After introducing the two relaxation oscillators, an all-digital PLL is
implemented for digital processing clock signal. In order to reduce power
consumption, the proposed ADPLL uses only a flip-flop as the phase detector.
The injection locked technique is implemented in this design for jitter
performance improvement. The measurement results show that the ADPLL
can approach 101 dBc/Hz at 100 kHz offset frequency. This design is
taped-out in GLOBALFOUDRIES 40-nm CMOS process, which only consume
about 1.2 mW at 1-GHz output frequency. In future work, it is going
to integrate the on-chip relaxation oscillator and digital PLL together to
create an entire on-chip clock generation and distribution system. |
| first_indexed | 2024-10-01T04:17:27Z |
| format | Thesis-Doctor of Philosophy |
| id | ntu-10356/70695 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T04:17:27Z |
| publishDate | 2017 |
| publisher | Nanyang Technological University |
| record_format | dspace |
| spelling | ntu-10356/706952020-11-01T04:51:33Z Low power clock generators with digital calibration for sustainable building applications Wang, Jiacheng Goh Wang Ling Interdisciplinary Graduate School (IGS) DRNTU::Engineering::Electrical and electronic engineering::Semiconductors The growth of human population on Earth has increased the awareness on the need for energy saving. The concept of smart building and life are proposed to connect all household appliances up to clouds to allow users to control these appliances with energy distribution in a smarter manner. With the expansion of mobile device usage and internet cloud applications, we are already moving to the big-data age. At the same time, the rapid developing digital signal processing technique requires the stable clock frequency due to different building environments, such as wide temperature range, variable supply voltage, sunshine time, humidity and so on. This thesis proposes two relaxation oscillator designs and an all-digital phase locked-loop (ADPLL) design as stable clock frequency generators for the sustainable building applications. The first proposed design presents a novel on-chip RC relaxation oscillator with split-capacitor integrator compensation loop technique to achieve a stable output frequency with environment temperature and supply voltage variations. It can provide a stable frequency signal at 13.5 MHz. Measurements results show that the output frequency has ±0.5% and ±0.5%/V variation with temperature range of −30◦C to 120◦C and power supply range of 1.5 − 2.1 V. Moreover, the power consumption of the design yields only 48.8 µW. The second design is also a relaxation oscillator with digital compensation technique to achieve a stable output frequency with environment temperature and supply voltage variations. The digital compensation scheme can avoid the power hungry analog op-amp integrator feedback loop. The digital method not only save more power in the long run, but is easier when comes to CMOS process scaling. Furthermore, an on-chip reference pulse generator is adopted for the compensation. The digital feedback loop tunes loop delay to adjust the output frequency. The test chips were fabricated in a 0.18- µm standard CMOS process. Effects of this digital compensation method has been verified to maintain frequency stability of the relaxation oscillator. The output frequency is stable at 12.77 MHz at 0.9-V power supply voltage. Measurement results showed that the output frequency has only 31ppm/◦C variation with temperature range of -30 to 120◦C after compensation. The frequency variation over the supply voltage is ±0.5%/V. Compared to other state-of-the-art designs, our design achieves better figure of merit (FoM) and has the smallest temperature coefficient. The total power consumption is 56.2 µW when all circuits are enabled. For long term operation, the power consumption can be scaled to only 12.8 µW in the main oscillator. After introducing the two relaxation oscillators, an all-digital PLL is implemented for digital processing clock signal. In order to reduce power consumption, the proposed ADPLL uses only a flip-flop as the phase detector. The injection locked technique is implemented in this design for jitter performance improvement. The measurement results show that the ADPLL can approach 101 dBc/Hz at 100 kHz offset frequency. This design is taped-out in GLOBALFOUDRIES 40-nm CMOS process, which only consume about 1.2 mW at 1-GHz output frequency. In future work, it is going to integrate the on-chip relaxation oscillator and digital PLL together to create an entire on-chip clock generation and distribution system. Doctor of Philosophy (IGS) 2017-05-09T06:24:18Z 2017-05-09T06:24:18Z 2017 Thesis-Doctor of Philosophy Wang, J. (2017). Low power clock generators with digital calibration for sustainable building applications. Doctoral thesis, Nanyang Technological University, Singapore. http://hdl.handle.net/10356/70695 10.32657/10356/70695 en 156 p. application/pdf Nanyang Technological University |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering::Semiconductors Wang, Jiacheng Low power clock generators with digital calibration for sustainable building applications |
| title | Low power clock generators with digital calibration for sustainable building applications |
| title_full | Low power clock generators with digital calibration for sustainable building applications |
| title_fullStr | Low power clock generators with digital calibration for sustainable building applications |
| title_full_unstemmed | Low power clock generators with digital calibration for sustainable building applications |
| title_short | Low power clock generators with digital calibration for sustainable building applications |
| title_sort | low power clock generators with digital calibration for sustainable building applications |
| topic | DRNTU::Engineering::Electrical and electronic engineering::Semiconductors |
| url | http://hdl.handle.net/10356/70695 |
| work_keys_str_mv | AT wangjiacheng lowpowerclockgeneratorswithdigitalcalibrationforsustainablebuildingapplications |