Subthreshold MOSFET voltage reference
This report presents the design of Low Dropout (LDO) Voltage Regulator, which is a circuit that can provide near constant voltage independent of supply voltage, temperature and loading variations. There are four designs included in this report starting from the design with poorest performance to the...
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| Format: | Final Year Project (FYP) |
| Language: | English |
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2017
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| Online Access: | http://hdl.handle.net/10356/71306 |
| _version_ | 1811686390516154368 |
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| author | Utomo, Nardi |
| author2 | Siek Liter |
| author_facet | Siek Liter Utomo, Nardi |
| author_sort | Utomo, Nardi |
| collection | NTU |
| description | This report presents the design of Low Dropout (LDO) Voltage Regulator, which is a circuit that can provide near constant voltage independent of supply voltage, temperature and loading variations. There are four designs included in this report starting from the design with poorest performance to the best performance. The final design consists of a start-up circuit, error amplifier (EA) with embedded voltage reference, and the temperature coefficient curvature correction circuit.
The design is simulated in Cadence Virtuoso environment with 0.18μm Global Foundries technology file. The proposed design can supply the voltage of 678 mV with minimum supply voltage of 700 mV. The design achieves excellent temperature coefficient (TC) of only 4.78 ppm/degC ranging from -50degC to 130degC. The design also achieves an extremely low load regulation of only 0.0011 mV/mA with maximum loading capability of 40 mA. The line regulation obtained is 16.24 mV/V. Solution has been proposed in the report that can further improve this value to 5.6 mV/V.
The design has good stability with phase margin above 100deg for both heavy load and light load conditions. The maximum undershoot and overshoot of the design are less than 135 mV with recovery time less than 3 μs. The total current used when the circuit is not driving any load is only 33.4 μA, which means the design does not consume large amount of power.
Finally, possible improvements to the design are discussed at the end of the report. Possible improvements include further improving the line regulation of the circuit and substituting remaining resistors with transistors while maintaining the circuit performance. Possible ways to do these are also mentioned at the end of this report. |
| first_indexed | 2024-10-01T04:59:39Z |
| format | Final Year Project (FYP) |
| id | ntu-10356/71306 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T04:59:39Z |
| publishDate | 2017 |
| record_format | dspace |
| spelling | ntu-10356/713062023-07-07T16:10:02Z Subthreshold MOSFET voltage reference Utomo, Nardi Siek Liter School of Electrical and Electronic Engineering Centre for Integrated Circuits and Systems DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits This report presents the design of Low Dropout (LDO) Voltage Regulator, which is a circuit that can provide near constant voltage independent of supply voltage, temperature and loading variations. There are four designs included in this report starting from the design with poorest performance to the best performance. The final design consists of a start-up circuit, error amplifier (EA) with embedded voltage reference, and the temperature coefficient curvature correction circuit. The design is simulated in Cadence Virtuoso environment with 0.18μm Global Foundries technology file. The proposed design can supply the voltage of 678 mV with minimum supply voltage of 700 mV. The design achieves excellent temperature coefficient (TC) of only 4.78 ppm/degC ranging from -50degC to 130degC. The design also achieves an extremely low load regulation of only 0.0011 mV/mA with maximum loading capability of 40 mA. The line regulation obtained is 16.24 mV/V. Solution has been proposed in the report that can further improve this value to 5.6 mV/V. The design has good stability with phase margin above 100deg for both heavy load and light load conditions. The maximum undershoot and overshoot of the design are less than 135 mV with recovery time less than 3 μs. The total current used when the circuit is not driving any load is only 33.4 μA, which means the design does not consume large amount of power. Finally, possible improvements to the design are discussed at the end of the report. Possible improvements include further improving the line regulation of the circuit and substituting remaining resistors with transistors while maintaining the circuit performance. Possible ways to do these are also mentioned at the end of this report. Bachelor of Engineering 2017-05-16T03:24:22Z 2017-05-16T03:24:22Z 2017 Final Year Project (FYP) http://hdl.handle.net/10356/71306 en Nanyang Technological University 83 p. application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits Utomo, Nardi Subthreshold MOSFET voltage reference |
| title | Subthreshold MOSFET voltage reference |
| title_full | Subthreshold MOSFET voltage reference |
| title_fullStr | Subthreshold MOSFET voltage reference |
| title_full_unstemmed | Subthreshold MOSFET voltage reference |
| title_short | Subthreshold MOSFET voltage reference |
| title_sort | subthreshold mosfet voltage reference |
| topic | DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits |
| url | http://hdl.handle.net/10356/71306 |
| work_keys_str_mv | AT utomonardi subthresholdmosfetvoltagereference |