Accelerating binary-matrix multiplication on FPGA
Matrix multiplication is required for a wide variety of applications, including data mining, linear algebra, graph transformations, etc. Most of the existing works to accelerate matrix multiplication have focused on matrices with integer and floating point elements. In this work, we proposed for the...
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| Other Authors: | |
| Format: | Final Year Project (FYP) |
| Language: | English |
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2017
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| Online Access: | http://hdl.handle.net/10356/72881 |
| _version_ | 1826126569079308288 |
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| author | Liwongan, Ricardo Jack |
| author2 | Anupam Chattopadhyay |
| author_facet | Anupam Chattopadhyay Liwongan, Ricardo Jack |
| author_sort | Liwongan, Ricardo Jack |
| collection | NTU |
| description | Matrix multiplication is required for a wide variety of applications, including data mining, linear algebra, graph transformations, etc. Most of the existing works to accelerate matrix multiplication have focused on matrices with integer and floating point elements. In this work, we proposed for the first time an FPGA-based accelerator architecture for binary matrix multiplication. It consists of processing elements laid out in regular tiled manner. The communication structure used is a torus. We undertook detailed experimental study of the proposed architecture. The architecture shows excellent scalability with increase in number of processing elements, with minimal drop in operating frequency. The proposed system achieves maximum throughput of 1084.37 Gops for 4x4 network size with 2048x2048 matrix size. The performance achieved by the system is considerably higher than existing works of integer and floating point matrix multiplications on FPGAs, due to optimized PE design for binary matrix multiplication. We also studied the impact of deploying efficient overlay Network-on-Chip (NoC) infrastructure to different aspects of our accelerator system. |
| first_indexed | 2024-10-01T06:54:47Z |
| format | Final Year Project (FYP) |
| id | ntu-10356/72881 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T06:54:47Z |
| publishDate | 2017 |
| record_format | dspace |
| spelling | ntu-10356/728812023-03-03T20:40:29Z Accelerating binary-matrix multiplication on FPGA Liwongan, Ricardo Jack Anupam Chattopadhyay School of Computer Science and Engineering DRNTU::Engineering::Computer science and engineering::Hardware Matrix multiplication is required for a wide variety of applications, including data mining, linear algebra, graph transformations, etc. Most of the existing works to accelerate matrix multiplication have focused on matrices with integer and floating point elements. In this work, we proposed for the first time an FPGA-based accelerator architecture for binary matrix multiplication. It consists of processing elements laid out in regular tiled manner. The communication structure used is a torus. We undertook detailed experimental study of the proposed architecture. The architecture shows excellent scalability with increase in number of processing elements, with minimal drop in operating frequency. The proposed system achieves maximum throughput of 1084.37 Gops for 4x4 network size with 2048x2048 matrix size. The performance achieved by the system is considerably higher than existing works of integer and floating point matrix multiplications on FPGAs, due to optimized PE design for binary matrix multiplication. We also studied the impact of deploying efficient overlay Network-on-Chip (NoC) infrastructure to different aspects of our accelerator system. Bachelor of Engineering (Computer Engineering) 2017-12-11T03:02:29Z 2017-12-11T03:02:29Z 2017 Final Year Project (FYP) http://hdl.handle.net/10356/72881 en Nanyang Technological University 59 p. application/pdf |
| spellingShingle | DRNTU::Engineering::Computer science and engineering::Hardware Liwongan, Ricardo Jack Accelerating binary-matrix multiplication on FPGA |
| title | Accelerating binary-matrix multiplication on FPGA |
| title_full | Accelerating binary-matrix multiplication on FPGA |
| title_fullStr | Accelerating binary-matrix multiplication on FPGA |
| title_full_unstemmed | Accelerating binary-matrix multiplication on FPGA |
| title_short | Accelerating binary-matrix multiplication on FPGA |
| title_sort | accelerating binary matrix multiplication on fpga |
| topic | DRNTU::Engineering::Computer science and engineering::Hardware |
| url | http://hdl.handle.net/10356/72881 |
| work_keys_str_mv | AT liwonganricardojack acceleratingbinarymatrixmultiplicationonfpga |