Design, verification and implementation of IEEE 1149.7 test access port
Standard access methods for Design for Testsbility (DfT) rely on the IEEE 1149.1 (JTAG) Test Access Port (TAP) controllers and associated collaterals. While the IEEE 1149.1 standard is a proven industry approach and has served the needs of DfT well, modern system on a chip (SoC) designs bring with i...
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| Format: | Thesis |
| Language: | English |
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2018
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| Online Access: | http://hdl.handle.net/10356/73131 |
| _version_ | 1826119182961344512 |
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| author | Ganesh Janani |
| author2 | Gwee Bah Hwee |
| author_facet | Gwee Bah Hwee Ganesh Janani |
| author_sort | Ganesh Janani |
| collection | NTU |
| description | Standard access methods for Design for Testsbility (DfT) rely on the IEEE 1149.1 (JTAG) Test Access Port (TAP) controllers and associated collaterals. While the IEEE 1149.1 standard is a proven industry approach and has served the needs of DfT well, modern system on a chip (SoC) designs bring with it additional challenges that require newer approaches to address them. IEEE 1149.7 (cJTAG) is one such standard that complements the existing IEEE 1149.1 standard to address some of the needs of SoC designs while adding newer features. It allows reduced pin count testing, chip-level bypass and individual direct addressing schemes, thereby incresing the test efficiency. To take advantage of the more efficient features, this dissertation seeks to design a Class 4 IEEE 1149.7 TAP Controller (T4 TAP.7C) that provides access to the embedded test blocks in a device using reduced pin TAP. An architecture of T4 TAP.7C has been proposed that supports both four-pin and two-pin TAP operation and provides 1-bit chip-level bypass. The design was implemented in System Verilog HDL. The designed T4 TAP.7C was verified using Cadence Incisive Enterprise Simulator and was synthesised using the Synopsys Design Compiler in a c28nm process. The proposed design was found to meet the required specifications and the maximum operating frequency supported in a c28nm process is ~1GHz. The designed T4 TAP.7C can be integrated into SoC development process to speed up the development of DfT architectures and design. |
| first_indexed | 2024-10-01T04:55:58Z |
| format | Thesis |
| id | ntu-10356/73131 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T04:55:58Z |
| publishDate | 2018 |
| record_format | dspace |
| spelling | ntu-10356/731312023-07-04T15:05:26Z Design, verification and implementation of IEEE 1149.7 test access port Ganesh Janani Gwee Bah Hwee School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering Standard access methods for Design for Testsbility (DfT) rely on the IEEE 1149.1 (JTAG) Test Access Port (TAP) controllers and associated collaterals. While the IEEE 1149.1 standard is a proven industry approach and has served the needs of DfT well, modern system on a chip (SoC) designs bring with it additional challenges that require newer approaches to address them. IEEE 1149.7 (cJTAG) is one such standard that complements the existing IEEE 1149.1 standard to address some of the needs of SoC designs while adding newer features. It allows reduced pin count testing, chip-level bypass and individual direct addressing schemes, thereby incresing the test efficiency. To take advantage of the more efficient features, this dissertation seeks to design a Class 4 IEEE 1149.7 TAP Controller (T4 TAP.7C) that provides access to the embedded test blocks in a device using reduced pin TAP. An architecture of T4 TAP.7C has been proposed that supports both four-pin and two-pin TAP operation and provides 1-bit chip-level bypass. The design was implemented in System Verilog HDL. The designed T4 TAP.7C was verified using Cadence Incisive Enterprise Simulator and was synthesised using the Synopsys Design Compiler in a c28nm process. The proposed design was found to meet the required specifications and the maximum operating frequency supported in a c28nm process is ~1GHz. The designed T4 TAP.7C can be integrated into SoC development process to speed up the development of DfT architectures and design. Master of Science (Integrated Circuit Design) 2018-01-03T07:12:47Z 2018-01-03T07:12:47Z 2018 Thesis http://hdl.handle.net/10356/73131 en 149 p. application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering Ganesh Janani Design, verification and implementation of IEEE 1149.7 test access port |
| title | Design, verification and implementation of IEEE 1149.7 test access port |
| title_full | Design, verification and implementation of IEEE 1149.7 test access port |
| title_fullStr | Design, verification and implementation of IEEE 1149.7 test access port |
| title_full_unstemmed | Design, verification and implementation of IEEE 1149.7 test access port |
| title_short | Design, verification and implementation of IEEE 1149.7 test access port |
| title_sort | design verification and implementation of ieee 1149 7 test access port |
| topic | DRNTU::Engineering::Electrical and electronic engineering |
| url | http://hdl.handle.net/10356/73131 |
| work_keys_str_mv | AT ganeshjanani designverificationandimplementationofieee11497testaccessport |