Speed up verification with hardware accelerator
The huge and never-stop-growing number of components integrated in System on Chip (SoC) makes the SoC increasingly complex. It also makes the normal ways of verification a bottleneck in the Integrated Circuit (IC) design process due to the cost and time-to-market requirement. The dissertation presen...
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| Format: | Thesis |
| Language: | English |
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2018
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| Online Access: | http://hdl.handle.net/10356/73137 |
| _version_ | 1824454083713433600 |
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| author | Liu, Yi |
| author2 | Chip Hong Chang |
| author_facet | Chip Hong Chang Liu, Yi |
| author_sort | Liu, Yi |
| collection | NTU |
| description | The huge and never-stop-growing number of components integrated in System on Chip (SoC) makes the SoC increasingly complex. It also makes the normal ways of verification a bottleneck in the Integrated Circuit (IC) design process due to the cost and time-to-market requirement. The dissertation presents the development of the transaction level communication component to speed up Global Navigation Satellite System (GNSS) boot load simulation based on a co-emulation environment which integrates the simulator and the Mentor Graphics’ emulator—Veloce2. The main task of this work is to build the TBX and get the boot load test passed. |
| first_indexed | 2025-02-19T03:16:41Z |
| format | Thesis |
| id | ntu-10356/73137 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2025-02-19T03:16:41Z |
| publishDate | 2018 |
| record_format | dspace |
| spelling | ntu-10356/731372023-07-04T15:05:29Z Speed up verification with hardware accelerator Liu, Yi Chip Hong Chang School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering The huge and never-stop-growing number of components integrated in System on Chip (SoC) makes the SoC increasingly complex. It also makes the normal ways of verification a bottleneck in the Integrated Circuit (IC) design process due to the cost and time-to-market requirement. The dissertation presents the development of the transaction level communication component to speed up Global Navigation Satellite System (GNSS) boot load simulation based on a co-emulation environment which integrates the simulator and the Mentor Graphics’ emulator—Veloce2. The main task of this work is to build the TBX and get the boot load test passed. Master of Science (Integrated Circuit Design) 2018-01-03T07:28:06Z 2018-01-03T07:28:06Z 2018 Thesis http://hdl.handle.net/10356/73137 en 67 p. application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering Liu, Yi Speed up verification with hardware accelerator |
| title | Speed up verification with hardware accelerator |
| title_full | Speed up verification with hardware accelerator |
| title_fullStr | Speed up verification with hardware accelerator |
| title_full_unstemmed | Speed up verification with hardware accelerator |
| title_short | Speed up verification with hardware accelerator |
| title_sort | speed up verification with hardware accelerator |
| topic | DRNTU::Engineering::Electrical and electronic engineering |
| url | http://hdl.handle.net/10356/73137 |
| work_keys_str_mv | AT liuyi speedupverificationwithhardwareaccelerator |