Design and implementation of a synthesizable test-bench for testing the LDPC decoder IP
In order to ascertain that for certain range of signal to noise ratio, the bit error ratio of the delivery LDPC IP core meets the requirement of the 2.5G Ethernet system, a fully synthesizable test-bench which can support both simulation and emulation environments, has been designed and implemented...
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| Format: | Thesis |
| Language: | English |
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2018
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| Online Access: | http://hdl.handle.net/10356/73139 |
| Summary: | In order to ascertain that for certain range of signal to noise ratio, the bit error ratio of the delivery LDPC IP core meets the requirement of the 2.5G Ethernet system, a fully synthesizable test-bench which can support both simulation and emulation environments, has been designed and implemented during the project period. The simulation environment is mainly used for preliminary and functional checks, and the emulation environment is chosen for further verification due to its much higher run speed compared to simulation. |
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