| Summary: | The Final Year Project aims to design a Digital Pulse Width Modulation (DPWM) generator and
evaluate the performance in terms of expected output signal and power consumption of the
generator while running at a high frequency. The generator is used as one of the fundamental
building block for a high speed DC-DC Converter in the future.
The DPWM generator operates at a supply voltage of 1.2V with a 5 bits resolution and runs at a
high speed of 100MHz. The process uses a 180nm CMOS technology. The design architecture of
the DPWM uses the methodologies of Hybrid DPWM which is the combination of Counter
together with the Tapped Delay Lines. Moreover, instead of injecting an external clock signal,
the DPWM is integrated with a Ring Oscillator that self generates a clock signal to the circuit.
The challenging part in the design is the timing and synchronization of every signal during the
time matching phase in order for the DPWM to operate in such high speed.
The report also looks into the comparison between a Ring Oscillator and RF Oscillator in terms
of supply sensitivity and power consumption. The report will explained how a Ring Oscillator is
more feasible for this PWM generator compare to the RF Oscillator.
In conclusion, the simulation result shows that the 5 bits DPWM could achieve 22 out of 32 valid
output signals at the operating frequency of 100MHz where the other outputs were either
distorted or could not be produced. Furthermore, the result also shows the feasibility of
integrating a Ring Oscillator that self generates a 400MHz clock signal for the DPWM. Lastly,
an interleave architecture was also recommended to improve the overall performance of the
DPWM in the future.
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