Low power supply module design of under voltage lock out circuit
The new era has witnessed the development of the process and technique in IC field. Power management ICs are growing strongly. With the development also comes the strict demanding of power consumption, hence a UVLO (Under Voltage Lock Out) circuit is proposed to meet the wide demands in power contro...
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| Otros Autores: | |
| Formato: | Tesis |
| Lenguaje: | English |
| Publicado: |
2018
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| Acceso en línea: | http://hdl.handle.net/10356/76074 |
| _version_ | 1826112442755710976 |
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| author | Zhao, Shuangdi |
| author2 | Siek Liter |
| author_facet | Siek Liter Zhao, Shuangdi |
| author_sort | Zhao, Shuangdi |
| collection | NTU |
| description | The new era has witnessed the development of the process and technique in IC field. Power management ICs are growing strongly. With the development also comes the strict demanding of power consumption, hence a UVLO (Under Voltage Lock Out) circuit is proposed to meet the wide demands in power control integrated circuit. In the design, the main modules include voltage reference, UVLO, LDO, and REFGOOD.
The proposed method is to regulate the supply voltage which is used to
enhance the supply rejection of the core circuit.
The global supply voltage (VCC) is 0V ~ 20V. With the increasing of VCC,
reference voltage ( V𝑟𝑒𝑓 ) in the core circuit will set up first. Moreover, PVT
compensation is represented to make the design of 𝑉ref capable of operating over different process, temperature and whole supply voltage.
There is a LDO module, of which the supply is VCC while the output (VDD) is the power source for other modules including UVLO and bandgap. When VCC reaches to around 5V, the local supply voltage (VDD) will be generated, which supply the power for the core circuit. The REF-GOOD signal stands for whether the voltage of LDO is ready. The UVLO module produces a rectangular signal with two different threshold voltages, satisfying the low power consumption and very low temperature draft.
It is designed in the C11HV Infineon 130nm BiCMOS Technology. The module architecture and circuit have already been optimized and simulated in the design. |
| first_indexed | 2024-10-01T03:07:05Z |
| format | Thesis |
| id | ntu-10356/76074 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T03:07:05Z |
| publishDate | 2018 |
| record_format | dspace |
| spelling | ntu-10356/760742023-07-04T15:41:27Z Low power supply module design of under voltage lock out circuit Zhao, Shuangdi Siek Liter School of Electrical and Electronic Engineering Technical University of Munich Gong Xiaowu DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits The new era has witnessed the development of the process and technique in IC field. Power management ICs are growing strongly. With the development also comes the strict demanding of power consumption, hence a UVLO (Under Voltage Lock Out) circuit is proposed to meet the wide demands in power control integrated circuit. In the design, the main modules include voltage reference, UVLO, LDO, and REFGOOD. The proposed method is to regulate the supply voltage which is used to enhance the supply rejection of the core circuit. The global supply voltage (VCC) is 0V ~ 20V. With the increasing of VCC, reference voltage ( V𝑟𝑒𝑓 ) in the core circuit will set up first. Moreover, PVT compensation is represented to make the design of 𝑉ref capable of operating over different process, temperature and whole supply voltage. There is a LDO module, of which the supply is VCC while the output (VDD) is the power source for other modules including UVLO and bandgap. When VCC reaches to around 5V, the local supply voltage (VDD) will be generated, which supply the power for the core circuit. The REF-GOOD signal stands for whether the voltage of LDO is ready. The UVLO module produces a rectangular signal with two different threshold voltages, satisfying the low power consumption and very low temperature draft. It is designed in the C11HV Infineon 130nm BiCMOS Technology. The module architecture and circuit have already been optimized and simulated in the design. Master of Science (Integrated Circuit Design) 2018-10-22T13:55:27Z 2018-10-22T13:55:27Z 2018 Thesis http://hdl.handle.net/10356/76074 en 73 p. application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits Zhao, Shuangdi Low power supply module design of under voltage lock out circuit |
| title | Low power supply module design of under voltage lock out circuit |
| title_full | Low power supply module design of under voltage lock out circuit |
| title_fullStr | Low power supply module design of under voltage lock out circuit |
| title_full_unstemmed | Low power supply module design of under voltage lock out circuit |
| title_short | Low power supply module design of under voltage lock out circuit |
| title_sort | low power supply module design of under voltage lock out circuit |
| topic | DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits |
| url | http://hdl.handle.net/10356/76074 |
| work_keys_str_mv | AT zhaoshuangdi lowpowersupplymoduledesignofundervoltagelockoutcircuit |