Switch cell optimization for power gated design
One of the key features for the success of hand-held devices is their low power consumption. For complex architecture and high frequency computation, reducing chip power dissipation has become ever more important. Various techniques like Multi threshold, dynamic voltage and frequency scaling (DVFS)...
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| Other Authors: | |
| Format: | Thesis |
| Language: | English |
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2018
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| Online Access: | http://hdl.handle.net/10356/76077 |
| _version_ | 1811685385247391744 |
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| author | Somani Ronak Kailashbhai |
| author2 | Lim Meng Hiot |
| author_facet | Lim Meng Hiot Somani Ronak Kailashbhai |
| author_sort | Somani Ronak Kailashbhai |
| collection | NTU |
| description | One of the key features for the success of hand-held devices is their low power consumption. For complex architecture and high frequency computation, reducing chip power dissipation has become ever more important. Various techniques like Multi threshold, dynamic voltage and frequency scaling (DVFS) and clock gating are used to limit the dynamic power. But for lower node technologies, leakage power has become a major contributing factor in total power and can no longer be neglected.
Power gating methodology is implemented to prevent leakage power dissipation. Switch cells turns on or off the power supply of a block, reducing leakage power. Implementing a power-gated block with optimized number of switch cells is vital to achieve power target. IR drop, turn-off power and area-overhead also depends on the number of switch cells inserted. Therefore, it is important to place an optimal number to meet performance, power and area desired. This dissertation attempts at finding the optimal number of switch cells by studying different parameters over a hardware design used for connected home application. |
| first_indexed | 2024-10-01T04:43:41Z |
| format | Thesis |
| id | ntu-10356/76077 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T04:43:41Z |
| publishDate | 2018 |
| record_format | dspace |
| spelling | ntu-10356/760772023-07-04T15:41:47Z Switch cell optimization for power gated design Somani Ronak Kailashbhai Lim Meng Hiot School of Electrical and Electronic Engineering Technical University of Munich DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits One of the key features for the success of hand-held devices is their low power consumption. For complex architecture and high frequency computation, reducing chip power dissipation has become ever more important. Various techniques like Multi threshold, dynamic voltage and frequency scaling (DVFS) and clock gating are used to limit the dynamic power. But for lower node technologies, leakage power has become a major contributing factor in total power and can no longer be neglected. Power gating methodology is implemented to prevent leakage power dissipation. Switch cells turns on or off the power supply of a block, reducing leakage power. Implementing a power-gated block with optimized number of switch cells is vital to achieve power target. IR drop, turn-off power and area-overhead also depends on the number of switch cells inserted. Therefore, it is important to place an optimal number to meet performance, power and area desired. This dissertation attempts at finding the optimal number of switch cells by studying different parameters over a hardware design used for connected home application. Master of Science (Integrated Circuit Design) 2018-10-23T00:05:18Z 2018-10-23T00:05:18Z 2018 Thesis http://hdl.handle.net/10356/76077 en 91 p. application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits Somani Ronak Kailashbhai Switch cell optimization for power gated design |
| title | Switch cell optimization for power gated design |
| title_full | Switch cell optimization for power gated design |
| title_fullStr | Switch cell optimization for power gated design |
| title_full_unstemmed | Switch cell optimization for power gated design |
| title_short | Switch cell optimization for power gated design |
| title_sort | switch cell optimization for power gated design |
| topic | DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits |
| url | http://hdl.handle.net/10356/76077 |
| work_keys_str_mv | AT somanironakkailashbhai switchcelloptimizationforpowergateddesign |