FPGA implementation of Kahan summation algorithm
In this project, Kahan Summation Algorithm, and an improved version of it, Kahan- Babuska Algorithm have been implemented in an FPGA platform to increase the accuracy in basic floating-point computation The Kahan Summation Algorithm is a method to add floating point numbers in a way to reduce the...
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| Other Authors: | |
| Format: | Final Year Project (FYP) |
| Language: | English |
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2018
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| Online Access: | http://hdl.handle.net/10356/76134 |
| _version_ | 1811694699950374912 |
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| author | Darshni, R |
| author2 | Smitha Kavallur Pisharath Gopi |
| author_facet | Smitha Kavallur Pisharath Gopi Darshni, R |
| author_sort | Darshni, R |
| collection | NTU |
| description | In this project, Kahan Summation Algorithm, and an improved version of it, Kahan-
Babuska Algorithm have been implemented in an FPGA platform to increase the
accuracy in basic floating-point computation The Kahan Summation Algorithm is a
method to add floating point numbers in a way to reduce the accumulation of error.
The designs are configurable to sum to 100 floating point numbers. There are two
implementations of the Kahan Summation Algorithm design, a purely blocking mode,
and a hybrid mode with pipelining. The Kahan-Babuska algorithm is implemented in
blocking mode. The designs have also been compared with each other, along with
software implementations to study the effectiveness of the implementation. |
| first_indexed | 2024-10-01T07:11:44Z |
| format | Final Year Project (FYP) |
| id | ntu-10356/76134 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T07:11:44Z |
| publishDate | 2018 |
| record_format | dspace |
| spelling | ntu-10356/761342023-03-03T20:40:22Z FPGA implementation of Kahan summation algorithm Darshni, R Smitha Kavallur Pisharath Gopi School of Computer Science and Engineering DRNTU::Engineering::Computer science and engineering In this project, Kahan Summation Algorithm, and an improved version of it, Kahan- Babuska Algorithm have been implemented in an FPGA platform to increase the accuracy in basic floating-point computation The Kahan Summation Algorithm is a method to add floating point numbers in a way to reduce the accumulation of error. The designs are configurable to sum to 100 floating point numbers. There are two implementations of the Kahan Summation Algorithm design, a purely blocking mode, and a hybrid mode with pipelining. The Kahan-Babuska algorithm is implemented in blocking mode. The designs have also been compared with each other, along with software implementations to study the effectiveness of the implementation. Bachelor of Engineering (Computer Engineering) 2018-11-19T08:27:26Z 2018-11-19T08:27:26Z 2018 Final Year Project (FYP) http://hdl.handle.net/10356/76134 en Nanyang Technological University 61 p. application/pdf |
| spellingShingle | DRNTU::Engineering::Computer science and engineering Darshni, R FPGA implementation of Kahan summation algorithm |
| title | FPGA implementation of Kahan summation algorithm |
| title_full | FPGA implementation of Kahan summation algorithm |
| title_fullStr | FPGA implementation of Kahan summation algorithm |
| title_full_unstemmed | FPGA implementation of Kahan summation algorithm |
| title_short | FPGA implementation of Kahan summation algorithm |
| title_sort | fpga implementation of kahan summation algorithm |
| topic | DRNTU::Engineering::Computer science and engineering |
| url | http://hdl.handle.net/10356/76134 |
| work_keys_str_mv | AT darshnir fpgaimplementationofkahansummationalgorithm |