Design of the asynchronous dynamic reference ADC
An 8 bits asynchronous dynamic reference analog to digital converter, ADC is introduced in this paper. The proposed ADC is a type of ADC that consists of N number of comparator/s for N number of bit/s and not governed by any clock signal. The whole design of the proposed ADC consists of 8 comparator...
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| 其他作者: | |
| 格式: | Final Year Project (FYP) |
| 语言: | English |
| 出版: |
2018
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| 主题: | |
| 在线阅读: | http://hdl.handle.net/10356/76267 |
| _version_ | 1826119518969135104 |
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| author | Sim, Jun Hwa |
| author2 | Siek Liter |
| author_facet | Siek Liter Sim, Jun Hwa |
| author_sort | Sim, Jun Hwa |
| collection | NTU |
| description | An 8 bits asynchronous dynamic reference analog to digital converter, ADC is introduced in this paper. The proposed ADC is a type of ADC that consists of N number of comparator/s for N number of bit/s and not governed by any clock signal. The whole design of the proposed ADC consists of 8 comparators, 7 current steering DACs and wide swing constant-transconductance bias circuit.
The proposed ADC is implemented with the aids of Cadence Virtuoso® Schematic Editor and Cadence Virtuoso® Analog Design Environment (ADE) with process technology of CHRT 0.18 µm. It is designed to convert an analog signal, which ranges from 0 V to 1 V, to an 8 bits digital signal.
The proposed ADC works under 1.8 V power supply and sampling frequency of 4 MHz. Under such specification, the ADC acquires 7.722 effective number of bits (ENOB), and power dissipated of 5.034 mWatt. In conclusion, performance of the ADC is measured by figure-of-merit, FOM of 5.96 pJ. |
| first_indexed | 2024-10-01T05:01:40Z |
| format | Final Year Project (FYP) |
| id | ntu-10356/76267 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T05:01:40Z |
| publishDate | 2018 |
| record_format | dspace |
| spelling | ntu-10356/762672023-07-07T17:13:37Z Design of the asynchronous dynamic reference ADC Sim, Jun Hwa Siek Liter School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering An 8 bits asynchronous dynamic reference analog to digital converter, ADC is introduced in this paper. The proposed ADC is a type of ADC that consists of N number of comparator/s for N number of bit/s and not governed by any clock signal. The whole design of the proposed ADC consists of 8 comparators, 7 current steering DACs and wide swing constant-transconductance bias circuit. The proposed ADC is implemented with the aids of Cadence Virtuoso® Schematic Editor and Cadence Virtuoso® Analog Design Environment (ADE) with process technology of CHRT 0.18 µm. It is designed to convert an analog signal, which ranges from 0 V to 1 V, to an 8 bits digital signal. The proposed ADC works under 1.8 V power supply and sampling frequency of 4 MHz. Under such specification, the ADC acquires 7.722 effective number of bits (ENOB), and power dissipated of 5.034 mWatt. In conclusion, performance of the ADC is measured by figure-of-merit, FOM of 5.96 pJ. Bachelor of Engineering (Electrical and Electronic Engineering) 2018-12-13T14:31:47Z 2018-12-13T14:31:47Z 2018 Final Year Project (FYP) http://hdl.handle.net/10356/76267 en Nanyang Technological University 68 p. application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering Sim, Jun Hwa Design of the asynchronous dynamic reference ADC |
| title | Design of the asynchronous dynamic reference ADC |
| title_full | Design of the asynchronous dynamic reference ADC |
| title_fullStr | Design of the asynchronous dynamic reference ADC |
| title_full_unstemmed | Design of the asynchronous dynamic reference ADC |
| title_short | Design of the asynchronous dynamic reference ADC |
| title_sort | design of the asynchronous dynamic reference adc |
| topic | DRNTU::Engineering::Electrical and electronic engineering |
| url | http://hdl.handle.net/10356/76267 |
| work_keys_str_mv | AT simjunhwa designoftheasynchronousdynamicreferenceadc |