Power management circuit for smart dust
This report pertains to design a digital pulse width modulator (DPWM) which can function at least 100MHz and has circuits of smaller area. The work is done to explore the differences of the structure of various types of DPWM, which are counter – based DPWM, tapped delay line (TDL) DPWM and hybrid DP...
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| Format: | Final Year Project (FYP) |
| Language: | English |
| Published: |
2019
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| Online Access: | http://hdl.handle.net/10356/77785 |
| _version_ | 1811686845941022720 |
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| author | Wong, Ken Khooi Lam |
| author2 | Gwee Bah Hwee |
| author_facet | Gwee Bah Hwee Wong, Ken Khooi Lam |
| author_sort | Wong, Ken Khooi Lam |
| collection | NTU |
| description | This report pertains to design a digital pulse width modulator (DPWM) which can function at least 100MHz and has circuits of smaller area. The work is done to explore the differences of the structure of various types of DPWM, which are counter – based DPWM, tapped delay line (TDL) DPWM and hybrid DPWM, and target for the design of DPWM which has circuits of smaller area and can be able to function in various range of frequencies in the future.
Cadence Virtuoso will be used to draw circuit diagram. ARM library which consists of most elements such as AND gate, OR gate, NOT gate, etc, will be deployed to design the DPWM. Various parts of subcircuits need to be designed such as a 100MHz-current-starved ring oscillator, 400MHz-current-starved ring oscillator, a delay chain, a 16-to-1 multiplexer (MUX), a bits justification block, and three output blocks. The process technology is 180nm CMOS, the supply voltage applied is 1.8V and the maximum simulation time is 40ns.
Three types of modified TDL DPWM have been proposed and compared, which are double – resetting TDL DPWM, low power TDL DPWM and high accuracy TDL DPWM. The DPWM outputs could be produced during rising edges and falling edges of the delayed 100MHz oscillation signal in all three types of modified TDL DPWM. A 16-to-1 MUX is applied instead of using 32-to-1 MUX and the number of delay elements and buffers in the delay chain has been reduced from 32 to 21.
From the simulation results, double resetting TDL DPWM dissipates the highest power meanwhile low power TDL DPWM dissipates the lowest power which is around 42.4% of the dissipated power of double resetting TDL DPWM. However, the difference between ideal pulse width and measured pulse width for each input is significant and the standard deviation of time gap of low power are the highest. For high accuracy TDL DPWM, the difference between ideal pulse width and measured pulse width for each input is very small and the standard deviation of time gap of low power are the lowest. |
| first_indexed | 2024-10-01T05:06:54Z |
| format | Final Year Project (FYP) |
| id | ntu-10356/77785 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T05:06:54Z |
| publishDate | 2019 |
| record_format | dspace |
| spelling | ntu-10356/777852023-07-07T16:07:30Z Power management circuit for smart dust Wong, Ken Khooi Lam Gwee Bah Hwee School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits This report pertains to design a digital pulse width modulator (DPWM) which can function at least 100MHz and has circuits of smaller area. The work is done to explore the differences of the structure of various types of DPWM, which are counter – based DPWM, tapped delay line (TDL) DPWM and hybrid DPWM, and target for the design of DPWM which has circuits of smaller area and can be able to function in various range of frequencies in the future. Cadence Virtuoso will be used to draw circuit diagram. ARM library which consists of most elements such as AND gate, OR gate, NOT gate, etc, will be deployed to design the DPWM. Various parts of subcircuits need to be designed such as a 100MHz-current-starved ring oscillator, 400MHz-current-starved ring oscillator, a delay chain, a 16-to-1 multiplexer (MUX), a bits justification block, and three output blocks. The process technology is 180nm CMOS, the supply voltage applied is 1.8V and the maximum simulation time is 40ns. Three types of modified TDL DPWM have been proposed and compared, which are double – resetting TDL DPWM, low power TDL DPWM and high accuracy TDL DPWM. The DPWM outputs could be produced during rising edges and falling edges of the delayed 100MHz oscillation signal in all three types of modified TDL DPWM. A 16-to-1 MUX is applied instead of using 32-to-1 MUX and the number of delay elements and buffers in the delay chain has been reduced from 32 to 21. From the simulation results, double resetting TDL DPWM dissipates the highest power meanwhile low power TDL DPWM dissipates the lowest power which is around 42.4% of the dissipated power of double resetting TDL DPWM. However, the difference between ideal pulse width and measured pulse width for each input is significant and the standard deviation of time gap of low power are the highest. For high accuracy TDL DPWM, the difference between ideal pulse width and measured pulse width for each input is very small and the standard deviation of time gap of low power are the lowest. Bachelor of Engineering (Electrical and Electronic Engineering) 2019-06-06T06:22:35Z 2019-06-06T06:22:35Z 2019 Final Year Project (FYP) http://hdl.handle.net/10356/77785 en Nanyang Technological University 136 p. application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits Wong, Ken Khooi Lam Power management circuit for smart dust |
| title | Power management circuit for smart dust |
| title_full | Power management circuit for smart dust |
| title_fullStr | Power management circuit for smart dust |
| title_full_unstemmed | Power management circuit for smart dust |
| title_short | Power management circuit for smart dust |
| title_sort | power management circuit for smart dust |
| topic | DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits |
| url | http://hdl.handle.net/10356/77785 |
| work_keys_str_mv | AT wongkenkhooilam powermanagementcircuitforsmartdust |