Timing mismatch calibration circuit for high-speed time-interleaved ADC
Time-Interleaved Analog-to-Digital Converter (TIADC) is a technique used to achieve a higher conversion speed of analog input signal to a digital output signal. Despite having an excellent operating frequency, this technique suffers from timing mismatch problem of the multiple channels of Analog-to-...
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| Format: | Final Year Project (FYP) |
| Language: | English |
| Published: |
2019
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| Online Access: | http://hdl.handle.net/10356/77891 |
| _version_ | 1826114475808260096 |
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| author | Seow, Yue Han |
| author2 | Gwee Bah Hwee |
| author_facet | Gwee Bah Hwee Seow, Yue Han |
| author_sort | Seow, Yue Han |
| collection | NTU |
| description | Time-Interleaved Analog-to-Digital Converter (TIADC) is a technique used to achieve a higher conversion speed of analog input signal to a digital output signal. Despite having an excellent operating frequency, this technique suffers from timing mismatch problem of the multiple channels of Analog-to-Digital converters (ADCs) used. This timing mismatch happens when each and every ADC in this system suffers a small delay in capturing the data from the input signal.
In this report, it consists of the working principle and theory behind the high speed TIADC system (2 GHz) and its main advantage compared to a single ADC system. However, the different weaknesses and mismatch problems encountered in this system are presented as well. The causes and effects of different mismatch problems like offset-mismatch, gain-mismatch and timing-mismatch are discussed in this report. The project then concentrated into the timing-mismatch problem of TIADC specifically. The method used to detect and correct the timing-mismatch problem is discussed and explained in the way to give the readers a clearer and brief understanding about it.
Mathematical solution is applied to address both the detection and correction of the timing-mismatch error. In the detection of timing-mismatch, mathematical functions like autocorrelation and least square criterion are executed. While in the correction of the timing-mismatch found, Lagrange Polynomial Interpolation is employed. In this project, Lagrange Polynomial Interpolation to the power of 4 is designed and implemented. |
| first_indexed | 2024-10-01T03:40:07Z |
| format | Final Year Project (FYP) |
| id | ntu-10356/77891 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T03:40:07Z |
| publishDate | 2019 |
| record_format | dspace |
| spelling | ntu-10356/778912023-07-07T18:05:57Z Timing mismatch calibration circuit for high-speed time-interleaved ADC Seow, Yue Han Gwee Bah Hwee School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering Time-Interleaved Analog-to-Digital Converter (TIADC) is a technique used to achieve a higher conversion speed of analog input signal to a digital output signal. Despite having an excellent operating frequency, this technique suffers from timing mismatch problem of the multiple channels of Analog-to-Digital converters (ADCs) used. This timing mismatch happens when each and every ADC in this system suffers a small delay in capturing the data from the input signal. In this report, it consists of the working principle and theory behind the high speed TIADC system (2 GHz) and its main advantage compared to a single ADC system. However, the different weaknesses and mismatch problems encountered in this system are presented as well. The causes and effects of different mismatch problems like offset-mismatch, gain-mismatch and timing-mismatch are discussed in this report. The project then concentrated into the timing-mismatch problem of TIADC specifically. The method used to detect and correct the timing-mismatch problem is discussed and explained in the way to give the readers a clearer and brief understanding about it. Mathematical solution is applied to address both the detection and correction of the timing-mismatch error. In the detection of timing-mismatch, mathematical functions like autocorrelation and least square criterion are executed. While in the correction of the timing-mismatch found, Lagrange Polynomial Interpolation is employed. In this project, Lagrange Polynomial Interpolation to the power of 4 is designed and implemented. Bachelor of Engineering (Electrical and Electronic Engineering) 2019-06-07T08:04:27Z 2019-06-07T08:04:27Z 2019 Final Year Project (FYP) http://hdl.handle.net/10356/77891 en Nanyang Technological University 65 p. application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering Seow, Yue Han Timing mismatch calibration circuit for high-speed time-interleaved ADC |
| title | Timing mismatch calibration circuit for high-speed time-interleaved ADC |
| title_full | Timing mismatch calibration circuit for high-speed time-interleaved ADC |
| title_fullStr | Timing mismatch calibration circuit for high-speed time-interleaved ADC |
| title_full_unstemmed | Timing mismatch calibration circuit for high-speed time-interleaved ADC |
| title_short | Timing mismatch calibration circuit for high-speed time-interleaved ADC |
| title_sort | timing mismatch calibration circuit for high speed time interleaved adc |
| topic | DRNTU::Engineering::Electrical and electronic engineering |
| url | http://hdl.handle.net/10356/77891 |
| work_keys_str_mv | AT seowyuehan timingmismatchcalibrationcircuitforhighspeedtimeinterleavedadc |