Frequency compensation in an input folded-cascode output buffered opamp with high PSRR
Low power low voltage systems are important aspect in every portable device. Powering up a device using a low voltage supply limits the maximum and minimum input voltage. To fully utilise a device with low voltage, the input voltage should be allowed to be as close as possible to the supply voltage....
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Final Year Project (FYP) |
| Language: | English |
| Published: |
2019
|
| Subjects: | |
| Online Access: | http://hdl.handle.net/10356/78162 |
| Summary: | Low power low voltage systems are important aspect in every portable device. Powering up a device using a low voltage supply limits the maximum and minimum input voltage. To fully utilise a device with low voltage, the input voltage should be allowed to be as close as possible to the supply voltage. This project presents op-amp design that enable rail-to-rail input and output stage. PMOS and NMOS differential pair are utilised as the input stage to achieve a rail-to-rail input stage. However, there exists a region where both transistors are on and causes gm to be nonconstant. Overlapping transition region technique is implemented to achieve a constant gm at the input stage. The designed circuit allows rail-to-rail input and output voltage with input stage gm variation of 5%-6%. Open-loop gain of 89.67dB and phase margin of 61.24° are achieved. Total Harmonic Distortion at fundamental frequency of 1kHz allows input voltage of 0.83Vpp at 0.01% or -80dB. CSM 0.18μm process technology is used in Cadence Custom IC Design Tools (Virtuoso Front to Back Design Environment) to complete this project. |
|---|