K-locked-loop and its application in time mode ADC
VCO is commonly used in time mode ADC to convert analog input voltage to time/phase information, where the time/phase information is subsequently converted to digital code using time-to-digital converter. Although high speed high resolution time-to-digital converters are currently available, the inh...
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| Format: | Conference Paper |
| Language: | English |
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2010
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| Online Access: | https://hdl.handle.net/10356/79867 http://hdl.handle.net/10220/6283 http://www.isic2009.org/ http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=5403964 |
| _version_ | 1826116510039408640 |
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| author | Hor, Hon Cheong Siek, Liter |
| author2 | School of Electrical and Electronic Engineering |
| author_facet | School of Electrical and Electronic Engineering Hor, Hon Cheong Siek, Liter |
| author_sort | Hor, Hon Cheong |
| collection | NTU |
| description | VCO is commonly used in time mode ADC to convert analog input voltage to time/phase information, where the time/phase information is subsequently converted to digital code using time-to-digital converter. Although high speed high resolution time-to-digital converters are currently available, the inherent nonlinear property of VCO however has become the bottle neck for time mode ADC. In this paper, a new concept named K-locked-loop is proposed to solve the nonlinearity issue of VCO within a time mode ADC. A 9-bit, 0.5MS/s time mode ADC has been modeled using SIMULINK tool in Matlab. Some of the circuits are simulated using Spectre simulator tool in Cadence using the 0.18μm CSM process, and the simulation result is back annotated to SIMULINK model to make the behavioral modeling more comprehensive and accurate. |
| first_indexed | 2024-10-01T04:12:34Z |
| format | Conference Paper |
| id | ntu-10356/79867 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T04:12:34Z |
| publishDate | 2010 |
| record_format | dspace |
| spelling | ntu-10356/798672019-12-06T13:35:41Z K-locked-loop and its application in time mode ADC Hor, Hon Cheong Siek, Liter School of Electrical and Electronic Engineering IEEE International Symposium on Integrated Circuits (12th : 2009 : Singapore) DRNTU::Engineering::Electrical and electronic engineering VCO is commonly used in time mode ADC to convert analog input voltage to time/phase information, where the time/phase information is subsequently converted to digital code using time-to-digital converter. Although high speed high resolution time-to-digital converters are currently available, the inherent nonlinear property of VCO however has become the bottle neck for time mode ADC. In this paper, a new concept named K-locked-loop is proposed to solve the nonlinearity issue of VCO within a time mode ADC. A 9-bit, 0.5MS/s time mode ADC has been modeled using SIMULINK tool in Matlab. Some of the circuits are simulated using Spectre simulator tool in Cadence using the 0.18μm CSM process, and the simulation result is back annotated to SIMULINK model to make the behavioral modeling more comprehensive and accurate. Published version 2010-05-11T01:26:24Z 2019-12-06T13:35:41Z 2010-05-11T01:26:24Z 2019-12-06T13:35:41Z 2009 2009 Conference Paper Hor, H. C., & Siek, L. (2009). Integrated Circuits, ISIC '09. In Proceedings of the 2009 12th International Symposium (pp.101-104). https://hdl.handle.net/10356/79867 http://hdl.handle.net/10220/6283 http://www.isic2009.org/ http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=5403964 en © 2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. 4 p. application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering Hor, Hon Cheong Siek, Liter K-locked-loop and its application in time mode ADC |
| title | K-locked-loop and its application in time mode ADC |
| title_full | K-locked-loop and its application in time mode ADC |
| title_fullStr | K-locked-loop and its application in time mode ADC |
| title_full_unstemmed | K-locked-loop and its application in time mode ADC |
| title_short | K-locked-loop and its application in time mode ADC |
| title_sort | k locked loop and its application in time mode adc |
| topic | DRNTU::Engineering::Electrical and electronic engineering |
| url | https://hdl.handle.net/10356/79867 http://hdl.handle.net/10220/6283 http://www.isic2009.org/ http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=5403964 |
| work_keys_str_mv | AT horhoncheong klockedloopanditsapplicationintimemodeadc AT siekliter klockedloopanditsapplicationintimemodeadc |