MixFX-SCORE: Heterogeneous Fixed-Point Compilation of Dataflow Computations
Mixed-precision implementation of computation can deliver area, throughput and power improvements for dataflow computations over homogeneous fixed-precision circuits without any loss in accuracy. When designing circuits for reconfigurable hardware, we can exercise independent control over bitwidth s...
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| Format: | Conference Paper |
| Language: | English |
| Published: |
2015
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| Online Access: | https://hdl.handle.net/10356/81246 http://hdl.handle.net/10220/39194 |
| _version_ | 1811689122290466816 |
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| author | Ye, Deheng Kapre, Nachiket |
| author2 | School of Computer Engineering |
| author_facet | School of Computer Engineering Ye, Deheng Kapre, Nachiket |
| author_sort | Ye, Deheng |
| collection | NTU |
| description | Mixed-precision implementation of computation can deliver area, throughput and power improvements for dataflow computations over homogeneous fixed-precision circuits without any loss in accuracy. When designing circuits for reconfigurable hardware, we can exercise independent control over bitwidth selection of each variable in the computation. However, selecting the best precision for each variable is an NP-hard problem. While traditional solutions use automated heuristics like simulated annealing or integer linear programming, they still rely on the manual formulation of resource models, which can be tedious, and potentially inaccurate due to the unpredictable interactions between different stages of the FPGA CAD flow. We develop MixFX-SCORE, an automated tool-flow based on FX-SCORE fixed-point compilation framework and simulated annealing, to address this challenge. We outsource error analysis (Gappa++) and resource model generation (Vivado HLS, Logic Synthesis, Xilinx Place-and-Route) to external tools that offer a more accurate representation of error behavior (backed by proofs) and resource usage (based on actual utilization). We demonstrate 1.1-3.5x LUTs count savings, 1-1.8x DSP count reductions, and 1-3.9x dynamic power improvements while still satisfying the accuracy constraints when compared to homogeneous fixed-point implementations. |
| first_indexed | 2024-10-01T05:43:05Z |
| format | Conference Paper |
| id | ntu-10356/81246 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T05:43:05Z |
| publishDate | 2015 |
| record_format | dspace |
| spelling | ntu-10356/812462020-05-28T07:18:12Z MixFX-SCORE: Heterogeneous Fixed-Point Compilation of Dataflow Computations Ye, Deheng Kapre, Nachiket School of Computer Engineering 2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Computer Science and Engineering Mixed-precision implementation of computation can deliver area, throughput and power improvements for dataflow computations over homogeneous fixed-precision circuits without any loss in accuracy. When designing circuits for reconfigurable hardware, we can exercise independent control over bitwidth selection of each variable in the computation. However, selecting the best precision for each variable is an NP-hard problem. While traditional solutions use automated heuristics like simulated annealing or integer linear programming, they still rely on the manual formulation of resource models, which can be tedious, and potentially inaccurate due to the unpredictable interactions between different stages of the FPGA CAD flow. We develop MixFX-SCORE, an automated tool-flow based on FX-SCORE fixed-point compilation framework and simulated annealing, to address this challenge. We outsource error analysis (Gappa++) and resource model generation (Vivado HLS, Logic Synthesis, Xilinx Place-and-Route) to external tools that offer a more accurate representation of error behavior (backed by proofs) and resource usage (based on actual utilization). We demonstrate 1.1-3.5x LUTs count savings, 1-1.8x DSP count reductions, and 1-3.9x dynamic power improvements while still satisfying the accuracy constraints when compared to homogeneous fixed-point implementations. Accepted version 2015-12-21T07:19:31Z 2019-12-06T14:26:27Z 2015-12-21T07:19:31Z 2019-12-06T14:26:27Z 2014 Conference Paper Ye, D., & Kapre, N. (2014). MixFX-SCORE: Heterogeneous Fixed-Point Compilation of Dataflow Computations. 2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines, 206-209. https://hdl.handle.net/10356/81246 http://hdl.handle.net/10220/39194 10.1109/FCCM.2014.64 en © 2014 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [http://dx.doi.org/10.1109/FCCM.2014.64]. 4 p. application/pdf |
| spellingShingle | Computer Science and Engineering Ye, Deheng Kapre, Nachiket MixFX-SCORE: Heterogeneous Fixed-Point Compilation of Dataflow Computations |
| title | MixFX-SCORE: Heterogeneous Fixed-Point Compilation of Dataflow Computations |
| title_full | MixFX-SCORE: Heterogeneous Fixed-Point Compilation of Dataflow Computations |
| title_fullStr | MixFX-SCORE: Heterogeneous Fixed-Point Compilation of Dataflow Computations |
| title_full_unstemmed | MixFX-SCORE: Heterogeneous Fixed-Point Compilation of Dataflow Computations |
| title_short | MixFX-SCORE: Heterogeneous Fixed-Point Compilation of Dataflow Computations |
| title_sort | mixfx score heterogeneous fixed point compilation of dataflow computations |
| topic | Computer Science and Engineering |
| url | https://hdl.handle.net/10356/81246 http://hdl.handle.net/10220/39194 |
| work_keys_str_mv | AT yedeheng mixfxscoreheterogeneousfixedpointcompilationofdataflowcomputations AT kaprenachiket mixfxscoreheterogeneousfixedpointcompilationofdataflowcomputations |