A Low Overhead Quasi-Delay-Insensitive (QDI) Asynchronous Data Path Synthesis Based on Microcell-Interleaving Genetic Algorithm (MIGA)
In this paper, we propose a design approach to mitigate the hardware overhead of the data completion detection circuit in quasi-delay-insensitive (QDI) asynchronous-logic circuits. In this proposed design approach, three novelties are highlighted. Firstly, a novel microcell-interleaving approach is...
| Main Authors: | , , , |
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| Other Authors: | |
| Format: | Journal Article |
| Language: | English |
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2015
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| Online Access: | https://hdl.handle.net/10356/81349 http://hdl.handle.net/10220/39226 |
| _version_ | 1826112694621569024 |
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| author | Zhou, Rong Chong, Kwen-Siong Chang, Joseph Sylvester Gwee, Bah Hwee |
| author2 | School of Electrical and Electronic Engineering |
| author_facet | School of Electrical and Electronic Engineering Zhou, Rong Chong, Kwen-Siong Chang, Joseph Sylvester Gwee, Bah Hwee |
| author_sort | Zhou, Rong |
| collection | NTU |
| description | In this paper, we propose a design approach to mitigate the hardware overhead of the data completion detection circuit in quasi-delay-insensitive (QDI) asynchronous-logic circuits. In this proposed design approach, three novelties are highlighted. Firstly, a novel microcell-interleaving approach is proposed to reduce the number of completion detection (CD) circuits while retaining the required QDI attribute. Secondly, we analyze the performance of the QDI circuits based on the proposed microcell-interleaving approach graphically in terms of power dissipation, transistor count and delay, and evaluate/determine the upper and lower boundaries of these performance profiles. Thirdly, we propose a microcell-interleaving genetic algorithm (MIGA) to stochastically optimize the proposed microcell-interleaving approach on power dissipation, transistor count, and delay. To validate the proposed design approach, a complete performance profile of ISCAS-85 C499 circuit is investigated on the basis of differential cascode voltage switch logic (DCVSL) and dynamic strong indicating (DSI) microcells. We demonstrate the efficiency of the proposed design approach by benchmarking against the competing DCVSL, null convention logic and DSI designs on five ISCAS-85 circuits. Specifically, the proposed designs, on average, are 1.77 × better in power dissipation, 1.4 × better in area, and 1.58 × better in a composite metric of power × area × delay, and reasonably slower for the lowest power dissipation points. We further demonstrate the practicality of the proposed design approach by implementing an 8-tap 16-bit asynchronous QDI finite impulse response filter. Finally, we demonstrate the ~10% and ~11% improved efficiency of the proposed MIGA over the greedy algorithm and dynamic programming, respectively. |
| first_indexed | 2024-10-01T03:11:08Z |
| format | Journal Article |
| id | ntu-10356/81349 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T03:11:08Z |
| publishDate | 2015 |
| record_format | dspace |
| spelling | ntu-10356/813492020-03-07T13:57:24Z A Low Overhead Quasi-Delay-Insensitive (QDI) Asynchronous Data Path Synthesis Based on Microcell-Interleaving Genetic Algorithm (MIGA) Zhou, Rong Chong, Kwen-Siong Chang, Joseph Sylvester Gwee, Bah Hwee School of Electrical and Electronic Engineering Genetic algorithm; input-complete Null convention logic (NCL) Input-complete Differential cascode voltage switch logic (DCVSL) Optimization Quasi-delay-insensitive (QDI) Asynchronous-logic In this paper, we propose a design approach to mitigate the hardware overhead of the data completion detection circuit in quasi-delay-insensitive (QDI) asynchronous-logic circuits. In this proposed design approach, three novelties are highlighted. Firstly, a novel microcell-interleaving approach is proposed to reduce the number of completion detection (CD) circuits while retaining the required QDI attribute. Secondly, we analyze the performance of the QDI circuits based on the proposed microcell-interleaving approach graphically in terms of power dissipation, transistor count and delay, and evaluate/determine the upper and lower boundaries of these performance profiles. Thirdly, we propose a microcell-interleaving genetic algorithm (MIGA) to stochastically optimize the proposed microcell-interleaving approach on power dissipation, transistor count, and delay. To validate the proposed design approach, a complete performance profile of ISCAS-85 C499 circuit is investigated on the basis of differential cascode voltage switch logic (DCVSL) and dynamic strong indicating (DSI) microcells. We demonstrate the efficiency of the proposed design approach by benchmarking against the competing DCVSL, null convention logic and DSI designs on five ISCAS-85 circuits. Specifically, the proposed designs, on average, are 1.77 × better in power dissipation, 1.4 × better in area, and 1.58 × better in a composite metric of power × area × delay, and reasonably slower for the lowest power dissipation points. We further demonstrate the practicality of the proposed design approach by implementing an 8-tap 16-bit asynchronous QDI finite impulse response filter. Finally, we demonstrate the ~10% and ~11% improved efficiency of the proposed MIGA over the greedy algorithm and dynamic programming, respectively. ASTAR (Agency for Sci., Tech. and Research, S’pore) Accepted version 2015-12-23T09:03:05Z 2019-12-06T14:28:58Z 2015-12-23T09:03:05Z 2019-12-06T14:28:58Z 2014 Journal Article Zhou, R., Chong, K.-S., Gwee, B. H., & Chang, J. S. (2014). A Low Overhead Quasi-Delay-Insensitive (QDI) Asynchronous Data Path Synthesis Based on Microcell-Interleaving Genetic Algorithm (MIGA). IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 33(7), 989-1002. 0278-0070 https://hdl.handle.net/10356/81349 http://hdl.handle.net/10220/39226 10.1109/TCAD.2014.2309859 en IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems © 2014 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [http://dx.doi.org/10.1109/TCAD.2014.2309859]. 16 p. application/pdf |
| spellingShingle | Genetic algorithm; input-complete Null convention logic (NCL) Input-complete Differential cascode voltage switch logic (DCVSL) Optimization Quasi-delay-insensitive (QDI) Asynchronous-logic Zhou, Rong Chong, Kwen-Siong Chang, Joseph Sylvester Gwee, Bah Hwee A Low Overhead Quasi-Delay-Insensitive (QDI) Asynchronous Data Path Synthesis Based on Microcell-Interleaving Genetic Algorithm (MIGA) |
| title | A Low Overhead Quasi-Delay-Insensitive (QDI) Asynchronous Data Path Synthesis Based on Microcell-Interleaving Genetic Algorithm (MIGA) |
| title_full | A Low Overhead Quasi-Delay-Insensitive (QDI) Asynchronous Data Path Synthesis Based on Microcell-Interleaving Genetic Algorithm (MIGA) |
| title_fullStr | A Low Overhead Quasi-Delay-Insensitive (QDI) Asynchronous Data Path Synthesis Based on Microcell-Interleaving Genetic Algorithm (MIGA) |
| title_full_unstemmed | A Low Overhead Quasi-Delay-Insensitive (QDI) Asynchronous Data Path Synthesis Based on Microcell-Interleaving Genetic Algorithm (MIGA) |
| title_short | A Low Overhead Quasi-Delay-Insensitive (QDI) Asynchronous Data Path Synthesis Based on Microcell-Interleaving Genetic Algorithm (MIGA) |
| title_sort | low overhead quasi delay insensitive qdi asynchronous data path synthesis based on microcell interleaving genetic algorithm miga |
| topic | Genetic algorithm; input-complete Null convention logic (NCL) Input-complete Differential cascode voltage switch logic (DCVSL) Optimization Quasi-delay-insensitive (QDI) Asynchronous-logic |
| url | https://hdl.handle.net/10356/81349 http://hdl.handle.net/10220/39226 |
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