Design of a Temperature-Aware Low-Voltage SRAM With Self-Adjustable Sensing Margin Enhancement for High-Temperature Applications up to 300 °C
This paper presents an 8-Kbit low-power SRAM for high-temperature (up to 300°C) applications. For reliable low-voltage operation, we employed a decoupled 8T SRAM cell structure. To minimize the performance variations caused by the wide operating temperate range, supply voltage was selected in the ne...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Journal Article |
| Language: | English |
| Published: |
2016
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/81733 http://hdl.handle.net/10220/39665 |
| Summary: | This paper presents an 8-Kbit low-power SRAM for high-temperature (up to 300°C) applications. For reliable low-voltage operation, we employed a decoupled 8T SRAM cell structure. To minimize the performance variations caused by the wide operating temperate range, supply voltage was selected in the near-threshold region. A temperature-aware bitline sensing margin enhancement technique is proposed to mitigate the impact of significantly increased bitline leakage on bitline swing and sensing window. A temperature-tracking control circuit generates bias voltage for optimal pull-up current for realizing the proposed enhancement technique. Test chips were fabricated in a commercial 5 V, 1.0 μm SOI technology. Test chip measurement demonstrates successful operation down to 2 V at 300°C. The average energy of 0.94 pJ was achieved at 2 V and 300°C. |
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