High Performance Low Overhead Template-based Cell-Interleave Pipeline (TCIP) for Asynchronous-Logic QDI Circuits
We propose a novel Template-based Cell-Interleave Pipeline (TCIP) approach for generating high performance and yet low overhead asynchronous-logic (async) quasi-delay-insensitive (QDI) circuits. Our TCIP approach exploits the characteristics of the four prevalent QDI cell templates, namely Weak-Cond...
| Main Authors: | , , , , , |
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| Other Authors: | |
| Format: | Conference Paper |
| Language: | English |
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2016
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| Online Access: | https://hdl.handle.net/10356/84007 http://hdl.handle.net/10220/41672 |
| _version_ | 1811676684819103744 |
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| author | Ho, Weng-Geng Liu, Nan Ne, Kyaw Zwa Lwin Chong, Kwen-Siong Gwee, Bah Hwee Chang, Joseph Sylvester |
| author2 | School of Electrical and Electronic Engineering |
| author_facet | School of Electrical and Electronic Engineering Ho, Weng-Geng Liu, Nan Ne, Kyaw Zwa Lwin Chong, Kwen-Siong Gwee, Bah Hwee Chang, Joseph Sylvester |
| author_sort | Ho, Weng-Geng |
| collection | NTU |
| description | We propose a novel Template-based Cell-Interleave Pipeline (TCIP) approach for generating high performance and yet low overhead asynchronous-logic (async) quasi-delay-insensitive (QDI) circuits. Our TCIP approach exploits the characteristics of the four prevalent QDI cell templates, namely Weak-Conditioned Half-Buffer (WCHB), Pre-Charged HalfBuffer (PCHB), Autonomous Signal-Validity Half-Buffer (ASVHB), and Sense-Amplifier Half-Buffer (SAHB), and then strategically interleave these template cells to form a composite pipeline. There are three main features in our TCIP approach. First, all QDI cell templates are first standardized with the same interface signals, and their corresponding cells are characterized in terms of transistor count, cycle time and energy dissipation for ease of comparison/selection/replacement. Second, our TCIP approach prioritizes the speed requirement when forming the initial pipeline circuits, and then subsequently reduces circuit overheads by interleaving various template cells without compromising the speed significantly. Third, the final optimized QDI pipeline circuit inherently features high robustness against process-voltage-temperature (PVT) variations, hence suitable for dynamic-voltage-scaling (DVS) operation. By means of 65nm CMOS process, we demonstrate a 4-bit pipeline tree adder based on the proposed TCIP approach, and benchmark it against the WCHB, PCHB, ASVHB and SAHB counterparts. These five designs feature same high operational robustness, nonetheless the design based on our TCIP approach is more competitive. Particularly, the designs based on reported approaches are, on average, ~1.22× more transistor count, ~1.21× slower and ~1.22× higher energy dissipation. Furthermore, under DVS operation from 1.2V to 0.3V, our proposed TCIP adder can reduce up to 88% energy for non-speed critical applications. |
| first_indexed | 2024-10-01T02:25:23Z |
| format | Conference Paper |
| id | ntu-10356/84007 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T02:25:23Z |
| publishDate | 2016 |
| record_format | dspace |
| spelling | ntu-10356/840072020-03-07T13:24:44Z High Performance Low Overhead Template-based Cell-Interleave Pipeline (TCIP) for Asynchronous-Logic QDI Circuits Ho, Weng-Geng Liu, Nan Ne, Kyaw Zwa Lwin Chong, Kwen-Siong Gwee, Bah Hwee Chang, Joseph Sylvester School of Electrical and Electronic Engineering IEEE International Symposium on Circuits and Systems (ISCAS) Centre for Integrated Circuits and Systems Voltage stabilizing circuits Asynchronous logic We propose a novel Template-based Cell-Interleave Pipeline (TCIP) approach for generating high performance and yet low overhead asynchronous-logic (async) quasi-delay-insensitive (QDI) circuits. Our TCIP approach exploits the characteristics of the four prevalent QDI cell templates, namely Weak-Conditioned Half-Buffer (WCHB), Pre-Charged HalfBuffer (PCHB), Autonomous Signal-Validity Half-Buffer (ASVHB), and Sense-Amplifier Half-Buffer (SAHB), and then strategically interleave these template cells to form a composite pipeline. There are three main features in our TCIP approach. First, all QDI cell templates are first standardized with the same interface signals, and their corresponding cells are characterized in terms of transistor count, cycle time and energy dissipation for ease of comparison/selection/replacement. Second, our TCIP approach prioritizes the speed requirement when forming the initial pipeline circuits, and then subsequently reduces circuit overheads by interleaving various template cells without compromising the speed significantly. Third, the final optimized QDI pipeline circuit inherently features high robustness against process-voltage-temperature (PVT) variations, hence suitable for dynamic-voltage-scaling (DVS) operation. By means of 65nm CMOS process, we demonstrate a 4-bit pipeline tree adder based on the proposed TCIP approach, and benchmark it against the WCHB, PCHB, ASVHB and SAHB counterparts. These five designs feature same high operational robustness, nonetheless the design based on our TCIP approach is more competitive. Particularly, the designs based on reported approaches are, on average, ~1.22× more transistor count, ~1.21× slower and ~1.22× higher energy dissipation. Furthermore, under DVS operation from 1.2V to 0.3V, our proposed TCIP adder can reduce up to 88% energy for non-speed critical applications. ASTAR (Agency for Sci., Tech. and Research, S’pore) Accepted version 2016-12-05T04:42:51Z 2019-12-06T15:36:20Z 2016-12-05T04:42:51Z 2019-12-06T15:36:20Z 2016 Conference Paper Ho, W.-G., Liu, N., Ne, K. Z. L., Chong, K.-S., Gwee, B. H., & Chang, J. S. (2016). High performance low overhead template-based Cell-Interleave Pipeline (TCIP) for asynchronous-logic QDI circuits. IEEE International Symposium on Circuits and Systems, 1762-1765. https://hdl.handle.net/10356/84007 http://hdl.handle.net/10220/41672 10.1109/ISCAS.2016.7538909 en © 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [http://dx.doi.org/10.1109/ISCAS.2016.7538909]. 4 p. application/pdf |
| spellingShingle | Voltage stabilizing circuits Asynchronous logic Ho, Weng-Geng Liu, Nan Ne, Kyaw Zwa Lwin Chong, Kwen-Siong Gwee, Bah Hwee Chang, Joseph Sylvester High Performance Low Overhead Template-based Cell-Interleave Pipeline (TCIP) for Asynchronous-Logic QDI Circuits |
| title | High Performance Low Overhead Template-based Cell-Interleave Pipeline (TCIP) for Asynchronous-Logic QDI Circuits |
| title_full | High Performance Low Overhead Template-based Cell-Interleave Pipeline (TCIP) for Asynchronous-Logic QDI Circuits |
| title_fullStr | High Performance Low Overhead Template-based Cell-Interleave Pipeline (TCIP) for Asynchronous-Logic QDI Circuits |
| title_full_unstemmed | High Performance Low Overhead Template-based Cell-Interleave Pipeline (TCIP) for Asynchronous-Logic QDI Circuits |
| title_short | High Performance Low Overhead Template-based Cell-Interleave Pipeline (TCIP) for Asynchronous-Logic QDI Circuits |
| title_sort | high performance low overhead template based cell interleave pipeline tcip for asynchronous logic qdi circuits |
| topic | Voltage stabilizing circuits Asynchronous logic |
| url | https://hdl.handle.net/10356/84007 http://hdl.handle.net/10220/41672 |
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