A 2.6–3.4 ghz fractional-N sub-sampling phase-locked loop using a calibration-free phase-switching-sub-sampling technique
Sub-sampling phase-locked loop (SSPLL) achieves lower in-band phase noise compared to a conventional charge-pump phase-locked loop with frequency dividers. Recently, several works have been reported to enable fractional-N operation of SSPLL to broaden its applications. However, they require careful...
| Main Authors: | , , , |
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| Other Authors: | |
| Format: | Journal Article |
| Language: | English |
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2019
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| Online Access: | https://hdl.handle.net/10356/85905 http://hdl.handle.net/10220/48325 |
| _version_ | 1826128639281856512 |
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| author | Liang, Zhipeng Yi, Xiang Yang, Kaituo Boon, Chirn Chye |
| author2 | School of Electrical and Electronic Engineering |
| author_facet | School of Electrical and Electronic Engineering Liang, Zhipeng Yi, Xiang Yang, Kaituo Boon, Chirn Chye |
| author_sort | Liang, Zhipeng |
| collection | NTU |
| description | Sub-sampling phase-locked loop (SSPLL) achieves lower in-band phase noise compared to a conventional charge-pump phase-locked loop with frequency dividers. Recently, several works have been reported to enable fractional-N operation of SSPLL to broaden its applications. However, they require careful calibrations with extra silicon area and adjusting time (20 ms measured) to achieve low phase noise. For scenarios requiring short settling time such as frequency modulation, such a time consuming calibration is undesirable. This letter presents a phase-switching technique for fractional-N mode SSPLL to eliminate this calibration. The principle of the technique is analyzed and a prototype is fabricated in 65-nm CMOS technology. Even without calibration, the frequency synthesizer achieves a figure of merit of -234.3 dB under fractional-N operation, with 13.3-mW power consumption at 1.2-V supply. |
| first_indexed | 2024-10-01T07:27:54Z |
| format | Journal Article |
| id | ntu-10356/85905 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T07:27:54Z |
| publishDate | 2019 |
| record_format | dspace |
| spelling | ntu-10356/859052020-03-07T13:57:29Z A 2.6–3.4 ghz fractional-N sub-sampling phase-locked loop using a calibration-free phase-switching-sub-sampling technique Liang, Zhipeng Yi, Xiang Yang, Kaituo Boon, Chirn Chye School of Electrical and Electronic Engineering Calibration Free CMOS Phase-Locked Loop DRNTU::Engineering::Electrical and electronic engineering Sub-sampling phase-locked loop (SSPLL) achieves lower in-band phase noise compared to a conventional charge-pump phase-locked loop with frequency dividers. Recently, several works have been reported to enable fractional-N operation of SSPLL to broaden its applications. However, they require careful calibrations with extra silicon area and adjusting time (20 ms measured) to achieve low phase noise. For scenarios requiring short settling time such as frequency modulation, such a time consuming calibration is undesirable. This letter presents a phase-switching technique for fractional-N mode SSPLL to eliminate this calibration. The principle of the technique is analyzed and a prototype is fabricated in 65-nm CMOS technology. Even without calibration, the frequency synthesizer achieves a figure of merit of -234.3 dB under fractional-N operation, with 13.3-mW power consumption at 1.2-V supply. MOE (Min. of Education, S’pore) Accepted version 2019-05-22T08:56:38Z 2019-12-06T16:12:25Z 2019-05-22T08:56:38Z 2019-12-06T16:12:25Z 2018 Journal Article Liang, Z., Yi, X., Yang, K., & Boon, C. C. (2018). A 2.6–3.4 ghz fractional-N sub-sampling phase-locked loop using a calibration-free phase-switching-sub-sampling technique. IEEE Microwave and Wireless Components Letters, 28(2), 147-149. doi:10.1109/LMWC.2017.2779889 1531-1309 https://hdl.handle.net/10356/85905 http://hdl.handle.net/10220/48325 10.1109/LMWC.2017.2779889 en IEEE Microwave and Wireless Components Letters © 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: https://doi.org/10.1109/LMWC.2017.2779889 3 p. application/pdf |
| spellingShingle | Calibration Free CMOS Phase-Locked Loop DRNTU::Engineering::Electrical and electronic engineering Liang, Zhipeng Yi, Xiang Yang, Kaituo Boon, Chirn Chye A 2.6–3.4 ghz fractional-N sub-sampling phase-locked loop using a calibration-free phase-switching-sub-sampling technique |
| title | A 2.6–3.4 ghz fractional-N sub-sampling phase-locked loop using a calibration-free phase-switching-sub-sampling technique |
| title_full | A 2.6–3.4 ghz fractional-N sub-sampling phase-locked loop using a calibration-free phase-switching-sub-sampling technique |
| title_fullStr | A 2.6–3.4 ghz fractional-N sub-sampling phase-locked loop using a calibration-free phase-switching-sub-sampling technique |
| title_full_unstemmed | A 2.6–3.4 ghz fractional-N sub-sampling phase-locked loop using a calibration-free phase-switching-sub-sampling technique |
| title_short | A 2.6–3.4 ghz fractional-N sub-sampling phase-locked loop using a calibration-free phase-switching-sub-sampling technique |
| title_sort | 2 6 3 4 ghz fractional n sub sampling phase locked loop using a calibration free phase switching sub sampling technique |
| topic | Calibration Free CMOS Phase-Locked Loop DRNTU::Engineering::Electrical and electronic engineering |
| url | https://hdl.handle.net/10356/85905 http://hdl.handle.net/10220/48325 |
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