Opportunistic design margining for area and power efficient processor pipelines in real time applications
The semiconductor industry is strategically focusing on automotive markets, and significant investment is targeted to addressing these markets. Runtime better-than-worst-case designs like Razor lead to massive timing errors upon breaching the critical operating point and have significant area overhe...
| Main Authors: | , , |
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| Other Authors: | |
| Format: | Journal Article |
| Language: | English |
| Published: |
2018
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/86547 http://hdl.handle.net/10220/45295 |
| _version_ | 1811682184101101568 |
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| author | Jayakrishnan, Mini Chang, Alan Kim, Tony Tae-Hyoung |
| author2 | School of Electrical and Electronic Engineering |
| author_facet | School of Electrical and Electronic Engineering Jayakrishnan, Mini Chang, Alan Kim, Tony Tae-Hyoung |
| author_sort | Jayakrishnan, Mini |
| collection | NTU |
| description | The semiconductor industry is strategically focusing on automotive markets, and significant investment is targeted to addressing these markets. Runtime better-than-worst-case designs like Razor lead to massive timing errors upon breaching the critical operating point and have significant area overheads. As we scale to higher-reliability automotive and industrial markets we need alternative techniques that will allow full extraction of the power benefits without sacrificing reliability. The proposed method utilizes positive slack available in the pipeline stages and re-distributes it to the preceding critical logic stage using Slack Balancing Flip-Flops (SBFFs). We use opportunistic under designing to get rid of the area, power and error correction overheads associated with the speculative hardware of runtime techniques. The proposed logic reshaping results in 12 percent and eight percent power and area savings respectively compared to the worst-case design approach. Compared to runtime better-than-worst-case designs, we get 51 percent and 10 percent power and area savings, respectively. In addition, the timing budgeting and timing correction using opportunistic slack eliminate critical operating point behavior, metastability issues and hold buffer overheads encountered in existing runtime resilience techniques. |
| first_indexed | 2024-10-01T03:52:48Z |
| format | Journal Article |
| id | ntu-10356/86547 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T03:52:48Z |
| publishDate | 2018 |
| record_format | dspace |
| spelling | ntu-10356/865472020-03-07T14:02:41Z Opportunistic design margining for area and power efficient processor pipelines in real time applications Jayakrishnan, Mini Chang, Alan Kim, Tony Tae-Hyoung School of Electrical and Electronic Engineering VIRTUS, IC Design Centre of Excellence Variation Tolerance Slack Balancing The semiconductor industry is strategically focusing on automotive markets, and significant investment is targeted to addressing these markets. Runtime better-than-worst-case designs like Razor lead to massive timing errors upon breaching the critical operating point and have significant area overheads. As we scale to higher-reliability automotive and industrial markets we need alternative techniques that will allow full extraction of the power benefits without sacrificing reliability. The proposed method utilizes positive slack available in the pipeline stages and re-distributes it to the preceding critical logic stage using Slack Balancing Flip-Flops (SBFFs). We use opportunistic under designing to get rid of the area, power and error correction overheads associated with the speculative hardware of runtime techniques. The proposed logic reshaping results in 12 percent and eight percent power and area savings respectively compared to the worst-case design approach. Compared to runtime better-than-worst-case designs, we get 51 percent and 10 percent power and area savings, respectively. In addition, the timing budgeting and timing correction using opportunistic slack eliminate critical operating point behavior, metastability issues and hold buffer overheads encountered in existing runtime resilience techniques. Published version 2018-07-27T03:54:56Z 2019-12-06T16:24:27Z 2018-07-27T03:54:56Z 2019-12-06T16:24:27Z 2018 Journal Article Jayakrishnan, M., Chang, A., & Kim, T. T.-H. (2018). Opportunistic design margining for area and power efficient processor pipelines in real time applications. Journal of Low Power Electronics and Applications, 8(2), 9-. 2079-9268 https://hdl.handle.net/10356/86547 http://hdl.handle.net/10220/45295 10.3390/jlpea8020009 en Journal of Low Power Electronics and Applications © 2018 The Author(s). Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/). 18 p. application/pdf |
| spellingShingle | Variation Tolerance Slack Balancing Jayakrishnan, Mini Chang, Alan Kim, Tony Tae-Hyoung Opportunistic design margining for area and power efficient processor pipelines in real time applications |
| title | Opportunistic design margining for area and power efficient processor pipelines in real time applications |
| title_full | Opportunistic design margining for area and power efficient processor pipelines in real time applications |
| title_fullStr | Opportunistic design margining for area and power efficient processor pipelines in real time applications |
| title_full_unstemmed | Opportunistic design margining for area and power efficient processor pipelines in real time applications |
| title_short | Opportunistic design margining for area and power efficient processor pipelines in real time applications |
| title_sort | opportunistic design margining for area and power efficient processor pipelines in real time applications |
| topic | Variation Tolerance Slack Balancing |
| url | https://hdl.handle.net/10356/86547 http://hdl.handle.net/10220/45295 |
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