A D-band amplifier in 65 nm bulk CMOS for short-distance data center communication
A novel pole-tuning technique with T-type network for interstage bandwidth extension is proposed in this paper. By exploiting the proposed technique in interstage of amplifiers, the transfer function of each stage exhibits two dominant poles, achieving a flat gain–frequency response over an ultrawid...
| Main Authors: | , , , , , , , |
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| Other Authors: | |
| Format: | Journal Article |
| Language: | English |
| Published: |
2018
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/89796 http://hdl.handle.net/10220/46393 |
| _version_ | 1811689407234703360 |
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| author | Huang, Qijun Yu, Hao Luo, Jiang He, Jin Feng, Guangyin Apriyana, Alit Fang, Ya Xue, Zhe |
| author2 | School of Electrical and Electronic Engineering |
| author_facet | School of Electrical and Electronic Engineering Huang, Qijun Yu, Hao Luo, Jiang He, Jin Feng, Guangyin Apriyana, Alit Fang, Ya Xue, Zhe |
| author_sort | Huang, Qijun |
| collection | NTU |
| description | A novel pole-tuning technique with T-type network for interstage bandwidth extension is proposed in this paper. By exploiting the proposed technique in interstage of amplifiers, the transfer function of each stage exhibits two dominant poles, achieving a flat gain–frequency response over an ultrawide bandwidth. For verification, a four-stage amplifier based on the pole-tuning technique with T-type network has been designed and implemented in a 65-nm bulk CMOS technology. The fabricated prototype achieves a peak gain of 9.5 dB at 122 GHz with a 3-dB bandwidth of more than 26 GHz and a fractional bandwidth of larger than 21.3%, while consuming a dc power of 62 mW. At the operating frequency of 125 GHz, the saturation output power and the output P 1 dB are 8.6 and 4.6 dBm, respectively. The chip occupies a small silicon area of 0.27 mm 2 including all testing pads with a core size of only 0.105 mm 2 . The proposed amplifier is suitable for short-distance data center communication as one of the key building blocks. |
| first_indexed | 2024-10-01T05:47:36Z |
| format | Journal Article |
| id | ntu-10356/89796 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T05:47:36Z |
| publishDate | 2018 |
| record_format | dspace |
| spelling | ntu-10356/897962020-03-07T13:57:31Z A D-band amplifier in 65 nm bulk CMOS for short-distance data center communication Huang, Qijun Yu, Hao Luo, Jiang He, Jin Feng, Guangyin Apriyana, Alit Fang, Ya Xue, Zhe School of Electrical and Electronic Engineering Millimeter-wave (mm-wave) CMOS DRNTU::Engineering::Electrical and electronic engineering A novel pole-tuning technique with T-type network for interstage bandwidth extension is proposed in this paper. By exploiting the proposed technique in interstage of amplifiers, the transfer function of each stage exhibits two dominant poles, achieving a flat gain–frequency response over an ultrawide bandwidth. For verification, a four-stage amplifier based on the pole-tuning technique with T-type network has been designed and implemented in a 65-nm bulk CMOS technology. The fabricated prototype achieves a peak gain of 9.5 dB at 122 GHz with a 3-dB bandwidth of more than 26 GHz and a fractional bandwidth of larger than 21.3%, while consuming a dc power of 62 mW. At the operating frequency of 125 GHz, the saturation output power and the output P 1 dB are 8.6 and 4.6 dBm, respectively. The chip occupies a small silicon area of 0.27 mm 2 including all testing pads with a core size of only 0.105 mm 2 . The proposed amplifier is suitable for short-distance data center communication as one of the key building blocks. Published version 2018-10-22T02:15:26Z 2019-12-06T17:33:42Z 2018-10-22T02:15:26Z 2019-12-06T17:33:42Z 2018 Journal Article Luo, J., He, J., Feng, G., Apriyana, A., Fang, Y., Xue, Z., . . . Yu, H. (2018). A D-band amplifier in 65 nm bulk CMOS for short-distance data center communication. IEEE Access, 6, 53191-53200. doi:10.1109/ACCESS.2018.2871047 https://hdl.handle.net/10356/89796 http://hdl.handle.net/10220/46393 10.1109/ACCESS.2018.2871047 en IEEE Access © 2018 IEEE. Translations and content mining are permitted for academic research only. Personal use is also permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. 10 p. application/pdf |
| spellingShingle | Millimeter-wave (mm-wave) CMOS DRNTU::Engineering::Electrical and electronic engineering Huang, Qijun Yu, Hao Luo, Jiang He, Jin Feng, Guangyin Apriyana, Alit Fang, Ya Xue, Zhe A D-band amplifier in 65 nm bulk CMOS for short-distance data center communication |
| title | A D-band amplifier in 65 nm bulk CMOS for short-distance data center communication |
| title_full | A D-band amplifier in 65 nm bulk CMOS for short-distance data center communication |
| title_fullStr | A D-band amplifier in 65 nm bulk CMOS for short-distance data center communication |
| title_full_unstemmed | A D-band amplifier in 65 nm bulk CMOS for short-distance data center communication |
| title_short | A D-band amplifier in 65 nm bulk CMOS for short-distance data center communication |
| title_sort | d band amplifier in 65 nm bulk cmos for short distance data center communication |
| topic | Millimeter-wave (mm-wave) CMOS DRNTU::Engineering::Electrical and electronic engineering |
| url | https://hdl.handle.net/10356/89796 http://hdl.handle.net/10220/46393 |
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