Chip temperature optimization for dark silicon many-core systems
In the dark silicon era, a fundamental problem is given a real-time computation demand, how to determine if an on-chip multiprocessor system is able to accept this demand and to maintain its reliability by keeping every core within a safe temperature range. In this paper, a practical thermal model i...
| Main Authors: | , , , , |
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| Other Authors: | |
| Format: | Journal Article |
| Language: | English |
| Published: |
2019
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/90105 http://hdl.handle.net/10220/48374 |
| _version_ | 1826119284032536576 |
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| author | Li, Mengquan Liu, Weichen Yang, Lei Chen, Peng Chen, Chao |
| author2 | School of Computer Science and Engineering |
| author_facet | School of Computer Science and Engineering Li, Mengquan Liu, Weichen Yang, Lei Chen, Peng Chen, Chao |
| author_sort | Li, Mengquan |
| collection | NTU |
| description | In the dark silicon era, a fundamental problem is given a real-time computation demand, how to determine if an on-chip multiprocessor system is able to accept this demand and to maintain its reliability by keeping every core within a safe temperature range. In this paper, a practical thermal model is described for quick chip temperature prediction. Integrated with the thermal model, we present a mixed integer linear programming (MILP) model to find the optimal task-to-core assignment with the minimum chip peak temperature. For the worst case where even the minimum chip peak temperature exceeds the safe temperature, a heuristic algorithm, called temperature-constrained task selection (TCTS), is proposed to optimize the system performance within chip safe temperature. The optimality of the TCTS algorithm is formally proven. Extensive performance evaluations show that our thermal model achieves an average prediction accuracy of 0.0741 °C within 0.2392 ms. The MILP model reduces chip peak temperature of ~10 °C comparing with traditional techniques. The system performance is increased by 19.8% under safe temperature limitation. Due to the satisfying scalability of our MILP formulation, the chip peak temperature is further decreased by 5.06 °C via the TCTS algorithm. The feasibility of this systematical technique is testified in a real case study as well. |
| first_indexed | 2024-10-01T04:57:43Z |
| format | Journal Article |
| id | ntu-10356/90105 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T04:57:43Z |
| publishDate | 2019 |
| record_format | dspace |
| spelling | ntu-10356/901052020-03-07T11:49:01Z Chip temperature optimization for dark silicon many-core systems Li, Mengquan Liu, Weichen Yang, Lei Chen, Peng Chen, Chao School of Computer Science and Engineering Dark Silicon Chip Temperature Optimization DRNTU::Engineering::Computer science and engineering In the dark silicon era, a fundamental problem is given a real-time computation demand, how to determine if an on-chip multiprocessor system is able to accept this demand and to maintain its reliability by keeping every core within a safe temperature range. In this paper, a practical thermal model is described for quick chip temperature prediction. Integrated with the thermal model, we present a mixed integer linear programming (MILP) model to find the optimal task-to-core assignment with the minimum chip peak temperature. For the worst case where even the minimum chip peak temperature exceeds the safe temperature, a heuristic algorithm, called temperature-constrained task selection (TCTS), is proposed to optimize the system performance within chip safe temperature. The optimality of the TCTS algorithm is formally proven. Extensive performance evaluations show that our thermal model achieves an average prediction accuracy of 0.0741 °C within 0.2392 ms. The MILP model reduces chip peak temperature of ~10 °C comparing with traditional techniques. The system performance is increased by 19.8% under safe temperature limitation. Due to the satisfying scalability of our MILP formulation, the chip peak temperature is further decreased by 5.06 °C via the TCTS algorithm. The feasibility of this systematical technique is testified in a real case study as well. Accepted version 2019-05-27T04:10:21Z 2019-12-06T17:40:46Z 2019-05-27T04:10:21Z 2019-12-06T17:40:46Z 2017 Journal Article Li, M., Liu, W., Yang, L., Chen, P., & Chen, C. (2018). Chip temperature optimization for dark silicon many-core systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 37(5), 941-953. doi:10.1109/TCAD.2017.2740306 0278-0070 https://hdl.handle.net/10356/90105 http://hdl.handle.net/10220/48374 10.1109/TCAD.2017.2740306 en IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems © 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: https://doi.org/10.1109/TCAD.2017.2740306. 13 p. application/pdf |
| spellingShingle | Dark Silicon Chip Temperature Optimization DRNTU::Engineering::Computer science and engineering Li, Mengquan Liu, Weichen Yang, Lei Chen, Peng Chen, Chao Chip temperature optimization for dark silicon many-core systems |
| title | Chip temperature optimization for dark silicon many-core systems |
| title_full | Chip temperature optimization for dark silicon many-core systems |
| title_fullStr | Chip temperature optimization for dark silicon many-core systems |
| title_full_unstemmed | Chip temperature optimization for dark silicon many-core systems |
| title_short | Chip temperature optimization for dark silicon many-core systems |
| title_sort | chip temperature optimization for dark silicon many core systems |
| topic | Dark Silicon Chip Temperature Optimization DRNTU::Engineering::Computer science and engineering |
| url | https://hdl.handle.net/10356/90105 http://hdl.handle.net/10220/48374 |
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