Power-efficient explicit-pulsed dual-edge triggered sense-amplifier flip-flops
A novel explicit-pulsed dual-edge triggered sense-amplifier flip-flop (DET-SAFF) for low-power and high-performance applications is presented in this paper. By incorporating...
| Glavni autori: | , , , |
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| Daljnji autori: | |
| Format: | Journal Article |
| Jezik: | English |
| Izdano: |
2010
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| Teme: | |
| Online pristup: | https://hdl.handle.net/10356/90676 http://hdl.handle.net/10220/6319 |
| Sažetak: | A novel explicit-pulsed dual-edge triggered sense-amplifier
flip-flop (DET-SAFF) for low-power and high-performance
applications is presented in this paper. By incorporating the
dual-edge triggering mechanism in the new fast latch and employing
conditional precharging, the DET-SAFF is able to achieve
low-power consumption that has small delay. To further reduce
the power consumption at low switching activities, a clock-gated
sense-amplifier (CG-SAFF) is engaged. Extensive post-layout
simulations proved that the proposed DET-SAFF exhibits both
the low-power and high-speed properties, with delay and power
reduction of up to 43.3% and 33.5% of those of the prior art,
respectively. When the switching activity is less than 0.5, the proposed
CG-SAFF demonstrates its superiority in terms of power
reduction. During zero input switching activity, CG-SAFF can
realize up to 86% in power saving. Lastly, a modification to the
proposed circuit has led to an improved common-mode rejection
ratio (CMRR) DET-SAFF. |
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