A scalable RFCMOS noise model
This paper presents the high-frequency (HF) noise...
| Main Authors: | , , , , |
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| Other Authors: | |
| Format: | Journal Article |
| Language: | English |
| Published: |
2010
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/90851 http://hdl.handle.net/10220/6245 |
| Summary: | This paper presents the high-frequency (HF) noise
modeling of an RF MOSFET for a 90-nm technology node. A
brief discussion on the noise measurement theory is presented to
illustrate the limitation of the noise measurement system. The extracted
noise sources were studied for their geometry and biasing
dependences and by implementing additional noise sources into
the small-signal RFCMOS model, accurate HF noise simulation
for the transistor can be achieved. Verilog-A is used for the coding
of the additional noise sources into the RFCMOS model and the
added noise source will compensate the underestimation of the
channel thermal noise from the BSIM3v3 core model. Simulated
noise circles and the measured noise figures are plotted at other
source impedances to show that all the noise parameters are
simulated accurately. The biasing and geometry dependences of
the measured and simulated noise parameters are presented to
demonstrate the scalability of the developed HF noise model. The
scalability feature in HF noise model can be implemented into
the process design kit (PDK) so that more powerful PDK can be
developed for the circuit designers to optimize and simulate their
circuit design that requires stringent noise specifications. The
accurate noise simulation can ensure better chance of success and
reduce the number of tape-out and design cycle time. |
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