Design and optimization of the extended true single-phase clock-based prescaler
The power consumption and operating frequency of the extended true single-phase clock (E-TSPC)-based frequency divider is investigated. The short-circuit power and the switching power in the E-TSPC-based divider are calculated and simulated. A low-power divide-by-2/3 unit of a prescaler is proposed...
| Main Authors: | , , , , |
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| Other Authors: | |
| Format: | Journal Article |
| Language: | English |
| Published: |
2009
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| Online Access: | https://hdl.handle.net/10356/91419 http://hdl.handle.net/10220/5950 |
| _version_ | 1826128783845883904 |
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| author | Yu, Xiao Peng Do, Manh Anh Lim, Wei Meng Yeo, Kiat Seng Ma, Jianguo |
| author2 | School of Electrical and Electronic Engineering |
| author_facet | School of Electrical and Electronic Engineering Yu, Xiao Peng Do, Manh Anh Lim, Wei Meng Yeo, Kiat Seng Ma, Jianguo |
| author_sort | Yu, Xiao Peng |
| collection | NTU |
| description | The power consumption and operating frequency of the extended true single-phase clock (E-TSPC)-based frequency divider is investigated. The short-circuit power and the switching power in the E-TSPC-based divider are calculated and simulated. A low-power divide-by-2/3 unit of a prescaler is proposed and implemented using a CMOS technology. Compared with the existing design, a 25% reduction of power consumption is achieved. A divide-by-8/9 dual-modulus prescaler implemented with this divide-by-2/3 unit using a 0.18-µm CMOS process is capable of operating up to 4 GHz with a low-power consumption. The prescaler is implemented in low-power high-resolution frequency dividers for wireless local area network applications. |
| first_indexed | 2024-10-01T07:30:13Z |
| format | Journal Article |
| id | ntu-10356/91419 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T07:30:13Z |
| publishDate | 2009 |
| record_format | dspace |
| spelling | ntu-10356/914192020-03-07T14:02:40Z Design and optimization of the extended true single-phase clock-based prescaler Yu, Xiao Peng Do, Manh Anh Lim, Wei Meng Yeo, Kiat Seng Ma, Jianguo School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering The power consumption and operating frequency of the extended true single-phase clock (E-TSPC)-based frequency divider is investigated. The short-circuit power and the switching power in the E-TSPC-based divider are calculated and simulated. A low-power divide-by-2/3 unit of a prescaler is proposed and implemented using a CMOS technology. Compared with the existing design, a 25% reduction of power consumption is achieved. A divide-by-8/9 dual-modulus prescaler implemented with this divide-by-2/3 unit using a 0.18-µm CMOS process is capable of operating up to 4 GHz with a low-power consumption. The prescaler is implemented in low-power high-resolution frequency dividers for wireless local area network applications. Published version 2009-07-31T06:26:26Z 2019-12-06T18:05:20Z 2009-07-31T06:26:26Z 2019-12-06T18:05:20Z 2006 2006 Journal Article Yu, X. P., Do, M. A., Lim, W. M., Yeo, K. S., & Ma, J. (2006). Design and optimization of the extended true single-phase clock-based prescaler. IEEE Transactions on Microwave Theory and Techniques, 54(11), 3828-3835. 0018-9480 https://hdl.handle.net/10356/91419 http://hdl.handle.net/10220/5950 10.1109/TMTT.2006.884629 en IEEE transactions on microwave theory and techniques IEEE Transactions on Microwave Theory and Techniques © 2006 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site. 8 p. application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering Yu, Xiao Peng Do, Manh Anh Lim, Wei Meng Yeo, Kiat Seng Ma, Jianguo Design and optimization of the extended true single-phase clock-based prescaler |
| title | Design and optimization of the extended true single-phase clock-based prescaler |
| title_full | Design and optimization of the extended true single-phase clock-based prescaler |
| title_fullStr | Design and optimization of the extended true single-phase clock-based prescaler |
| title_full_unstemmed | Design and optimization of the extended true single-phase clock-based prescaler |
| title_short | Design and optimization of the extended true single-phase clock-based prescaler |
| title_sort | design and optimization of the extended true single phase clock based prescaler |
| topic | DRNTU::Engineering::Electrical and electronic engineering |
| url | https://hdl.handle.net/10356/91419 http://hdl.handle.net/10220/5950 |
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