A low-power 16×16-b parallel multiplier utilizing pass-transistor logic
This paper describes a low-power 16x16-b parallel very large scale integration multiplier, designed and fabricated using a 0.8- m double-metal double-poly BiCMOS process. In order to achieve low-power operation, the multiplier was designed utilizing mainly pass-transistor (PT) logic circuits. The in...
| Үндсэн зохиолчид: | , , |
|---|---|
| Формат: | Journal Article |
| Хэл сонгох: | English |
| Хэвлэсэн: |
2009
|
| Нөхцлүүд: | |
| Онлайн хандалт: | https://hdl.handle.net/10356/91516 http://hdl.handle.net/10220/6009 |
| _version_ | 1826113761213153280 |
|---|---|
| author | Law, C. F. Rofail, Samir S. Yeo, Kiat Seng |
| author_facet | Law, C. F. Rofail, Samir S. Yeo, Kiat Seng |
| author_sort | Law, C. F. |
| collection | NTU |
| description | This paper describes a low-power 16x16-b parallel very large scale integration multiplier, designed and fabricated using a 0.8- m double-metal double-poly BiCMOS process. In order to achieve low-power operation, the multiplier was designed utilizing mainly pass-transistor (PT) logic circuits. The inherent nonfull-swing nature of PT logic circuits were taken full advantage of, without significantly compromising the speed performance of the overall circuit implementation. New circuit implementations for the partial-product generator and the partial-product addition circuitry have been proposed, simulated, and fabricated. Experimental results showed that the worst case multiplication time of the test chip is 10.4 ns at a supply voltage of 3.3 V, and the average power dissipation is 38 mW at a frequency of 10 MHz. |
| first_indexed | 2024-10-01T03:28:11Z |
| format | Journal Article |
| id | ntu-10356/91516 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T03:28:11Z |
| publishDate | 2009 |
| record_format | dspace |
| spelling | ntu-10356/915162020-03-07T14:02:40Z A low-power 16×16-b parallel multiplier utilizing pass-transistor logic Law, C. F. Rofail, Samir S. Yeo, Kiat Seng DRNTU::Engineering::Electrical and electronic engineering This paper describes a low-power 16x16-b parallel very large scale integration multiplier, designed and fabricated using a 0.8- m double-metal double-poly BiCMOS process. In order to achieve low-power operation, the multiplier was designed utilizing mainly pass-transistor (PT) logic circuits. The inherent nonfull-swing nature of PT logic circuits were taken full advantage of, without significantly compromising the speed performance of the overall circuit implementation. New circuit implementations for the partial-product generator and the partial-product addition circuitry have been proposed, simulated, and fabricated. Experimental results showed that the worst case multiplication time of the test chip is 10.4 ns at a supply voltage of 3.3 V, and the average power dissipation is 38 mW at a frequency of 10 MHz. Published version 2009-08-03T04:45:40Z 2019-12-06T18:07:05Z 2009-08-03T04:45:40Z 2019-12-06T18:07:05Z 1999 1999 Journal Article Law, C. F., Rofail, S. S., & Yeo., K. S. (1999). A low-power 16 16-b parallel multiplier utilizing pass-transistor logic. IEEE Journal of Solid-State Circuits, 34(10), 1395-1399. 0018-9200 https://hdl.handle.net/10356/91516 http://hdl.handle.net/10220/6009 10.1109/4.792613 en IEEE journal of solid-state circuits IEEE Journal of Solid-State Circuits © 1999 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site. 5 p. application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering Law, C. F. Rofail, Samir S. Yeo, Kiat Seng A low-power 16×16-b parallel multiplier utilizing pass-transistor logic |
| title | A low-power 16×16-b parallel multiplier utilizing pass-transistor logic |
| title_full | A low-power 16×16-b parallel multiplier utilizing pass-transistor logic |
| title_fullStr | A low-power 16×16-b parallel multiplier utilizing pass-transistor logic |
| title_full_unstemmed | A low-power 16×16-b parallel multiplier utilizing pass-transistor logic |
| title_short | A low-power 16×16-b parallel multiplier utilizing pass-transistor logic |
| title_sort | low power 16 16 b parallel multiplier utilizing pass transistor logic |
| topic | DRNTU::Engineering::Electrical and electronic engineering |
| url | https://hdl.handle.net/10356/91516 http://hdl.handle.net/10220/6009 |
| work_keys_str_mv | AT lawcf alowpower1616bparallelmultiplierutilizingpasstransistorlogic AT rofailsamirs alowpower1616bparallelmultiplierutilizingpasstransistorlogic AT yeokiatseng alowpower1616bparallelmultiplierutilizingpasstransistorlogic AT lawcf lowpower1616bparallelmultiplierutilizingpasstransistorlogic AT rofailsamirs lowpower1616bparallelmultiplierutilizingpasstransistorlogic AT yeokiatseng lowpower1616bparallelmultiplierutilizingpasstransistorlogic |