A 4.06 mW 10-bit 150 MS/s SAR ADC with 1.5-bit/cycle operation for medical imaging applications
This paper reports a 10-bit 150 MS/s successive approximation register analog-to-digital converter with binary-scaled redundancy-facilitated error correction technique. The proposed 1.5-bit/cycle technique with built-in capacitive digital-to-analog converter (CDAC) redundancy, corrects multiple erro...
| Main Authors: | , , |
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| Other Authors: | |
| Format: | Journal Article |
| Language: | English |
| Published: |
2019
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/92451 http://hdl.handle.net/10220/49924 |
| _version_ | 1826109434954252288 |
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| author | Sunny, Sharma Chen, Yong Boon, Chirn Chye |
| author2 | School of Electrical and Electronic Engineering |
| author_facet | School of Electrical and Electronic Engineering Sunny, Sharma Chen, Yong Boon, Chirn Chye |
| author_sort | Sunny, Sharma |
| collection | NTU |
| description | This paper reports a 10-bit 150 MS/s successive approximation register analog-to-digital converter with binary-scaled redundancy-facilitated error correction technique. The proposed 1.5-bit/cycle technique with built-in capacitive digital-to-analog converter (CDAC) redundancy, corrects multiple erroneous decisions in a total of nine conversion cycles. The proposed binary-scaled redundancy provides a 12.5% error tolerance range for the incomplete CDAC voltage settling. The digital error-correction logic circuit presented uses a bit-overlap-and-add technique. The prototype chip was fabricated in 65-nm CMOS technology and occupies chip area of 0.038 mm 2 . It consumes 4.06 mW from a 1.2 V supply, achieving the Nyquist signal-to-noise-and-distortion ratio of 57.81 dB and the effective number of bits of 9.31-bit at an operating frequency of 150 MS/s, corresponding to the figure-of-merit of 42.6 fJ/ conversion-step. |
| first_indexed | 2024-10-01T02:18:10Z |
| format | Journal Article |
| id | ntu-10356/92451 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T02:18:10Z |
| publishDate | 2019 |
| record_format | dspace |
| spelling | ntu-10356/924512020-03-07T14:02:41Z A 4.06 mW 10-bit 150 MS/s SAR ADC with 1.5-bit/cycle operation for medical imaging applications Sunny, Sharma Chen, Yong Boon, Chirn Chye School of Electrical and Electronic Engineering 1.5-bit/cycle ADC Engineering::Electrical and electronic engineering This paper reports a 10-bit 150 MS/s successive approximation register analog-to-digital converter with binary-scaled redundancy-facilitated error correction technique. The proposed 1.5-bit/cycle technique with built-in capacitive digital-to-analog converter (CDAC) redundancy, corrects multiple erroneous decisions in a total of nine conversion cycles. The proposed binary-scaled redundancy provides a 12.5% error tolerance range for the incomplete CDAC voltage settling. The digital error-correction logic circuit presented uses a bit-overlap-and-add technique. The prototype chip was fabricated in 65-nm CMOS technology and occupies chip area of 0.038 mm 2 . It consumes 4.06 mW from a 1.2 V supply, achieving the Nyquist signal-to-noise-and-distortion ratio of 57.81 dB and the effective number of bits of 9.31-bit at an operating frequency of 150 MS/s, corresponding to the figure-of-merit of 42.6 fJ/ conversion-step. Accepted version 2019-09-11T08:49:38Z 2019-12-06T18:23:31Z 2019-09-11T08:49:38Z 2019-12-06T18:23:31Z 2018 Journal Article Sunny, S., Chen, Y., & Boon, C. C. (2018). A 4.06 mW 10-bit 150 MS/s SAR ADC with 1.5-bit/cycle operation for medical imaging applications. IEEE Sensors Journal, 18(11), 4553-4560. doi:10.1109/JSEN.2018.2825400 1530-437X https://hdl.handle.net/10356/92451 http://hdl.handle.net/10220/49924 10.1109/JSEN.2018.2825400 en IEEE Sensors Journal © 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: https://doi.org/10.1109/JSEN.2018.2825400. 8 p. application/pdf |
| spellingShingle | 1.5-bit/cycle ADC Engineering::Electrical and electronic engineering Sunny, Sharma Chen, Yong Boon, Chirn Chye A 4.06 mW 10-bit 150 MS/s SAR ADC with 1.5-bit/cycle operation for medical imaging applications |
| title | A 4.06 mW 10-bit 150 MS/s SAR ADC with 1.5-bit/cycle operation for medical imaging applications |
| title_full | A 4.06 mW 10-bit 150 MS/s SAR ADC with 1.5-bit/cycle operation for medical imaging applications |
| title_fullStr | A 4.06 mW 10-bit 150 MS/s SAR ADC with 1.5-bit/cycle operation for medical imaging applications |
| title_full_unstemmed | A 4.06 mW 10-bit 150 MS/s SAR ADC with 1.5-bit/cycle operation for medical imaging applications |
| title_short | A 4.06 mW 10-bit 150 MS/s SAR ADC with 1.5-bit/cycle operation for medical imaging applications |
| title_sort | 4 06 mw 10 bit 150 ms s sar adc with 1 5 bit cycle operation for medical imaging applications |
| topic | 1.5-bit/cycle ADC Engineering::Electrical and electronic engineering |
| url | https://hdl.handle.net/10356/92451 http://hdl.handle.net/10220/49924 |
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