A 4.06 mW 10-bit 150 MS/s SAR ADC with 1.5-bit/cycle operation for medical imaging applications
This paper reports a 10-bit 150 MS/s successive approximation register analog-to-digital converter with binary-scaled redundancy-facilitated error correction technique. The proposed 1.5-bit/cycle technique with built-in capacitive digital-to-analog converter (CDAC) redundancy, corrects multiple erro...
| Main Authors: | , , |
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| Other Authors: | |
| Format: | Journal Article |
| Language: | English |
| Published: |
2019
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/92451 http://hdl.handle.net/10220/49924 |