Design and analysis of double-gate MOSFETs for ultra-low power radio frequency identification (RFID) : device and circuit co-design
Recently, double-gate MOSFETs (DGMOSFETs) have been shown to be more otpimal for ultra-low power circuit design due to the improved subthreshold slope and the reduced leakage current compared to bulk CMOS. However, DGMOSFETs for subthreshold circuit design have not been much explored in comparison t...
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| Other Authors: | |
| Format: | Journal Article |
| Language: | English |
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2012
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| Online Access: | https://hdl.handle.net/10356/94092 http://hdl.handle.net/10220/7491 |
| _version_ | 1811691130281000960 |
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| author | Vaddi, Ramesh. Agarwal, Rajendra P. Dasgupta, Sudeb. Kim, Tony Tae-Hyoung |
| author2 | School of Electrical and Electronic Engineering |
| author_facet | School of Electrical and Electronic Engineering Vaddi, Ramesh. Agarwal, Rajendra P. Dasgupta, Sudeb. Kim, Tony Tae-Hyoung |
| author_sort | Vaddi, Ramesh. |
| collection | NTU |
| description | Recently, double-gate MOSFETs (DGMOSFETs) have been shown to be more otpimal for ultra-low power circuit design due to the improved subthreshold slope and the reduced leakage current compared to bulk CMOS. However, DGMOSFETs for subthreshold circuit design have not been much explored in comparison to those for string inversion-based design. In this paper, various configurations of DGMOSFETs, such as tied/independent gates and symmetric/asymmetric gate oxide thicknes are explored for ultra-low power and high efficient radio frequency identification (RFID) design. Comparison of bulk CMOS with DGMOSFETs has been conducted in ultra-low power subthreshold digital logic design and rectifier desgin, emphasizing the scope of the nano-scale DGMOSFET technology for future ultra-low power systems. The DGMOSFET-based subthreshold logic improves energy efficiency by more than 40% compared to the bulk CMOS-based logic at 32nm. Among the various DGMOSFET configurations for RFID rectifiers, symmetric tied-gate DGMOSFET has the best power conversion efficiency and the lowest power consumption. |
| first_indexed | 2024-10-01T06:15:00Z |
| format | Journal Article |
| id | ntu-10356/94092 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T06:15:00Z |
| publishDate | 2012 |
| record_format | dspace |
| spelling | ntu-10356/940922020-03-07T14:02:43Z Design and analysis of double-gate MOSFETs for ultra-low power radio frequency identification (RFID) : device and circuit co-design Vaddi, Ramesh. Agarwal, Rajendra P. Dasgupta, Sudeb. Kim, Tony Tae-Hyoung School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits Recently, double-gate MOSFETs (DGMOSFETs) have been shown to be more otpimal for ultra-low power circuit design due to the improved subthreshold slope and the reduced leakage current compared to bulk CMOS. However, DGMOSFETs for subthreshold circuit design have not been much explored in comparison to those for string inversion-based design. In this paper, various configurations of DGMOSFETs, such as tied/independent gates and symmetric/asymmetric gate oxide thicknes are explored for ultra-low power and high efficient radio frequency identification (RFID) design. Comparison of bulk CMOS with DGMOSFETs has been conducted in ultra-low power subthreshold digital logic design and rectifier desgin, emphasizing the scope of the nano-scale DGMOSFET technology for future ultra-low power systems. The DGMOSFET-based subthreshold logic improves energy efficiency by more than 40% compared to the bulk CMOS-based logic at 32nm. Among the various DGMOSFET configurations for RFID rectifiers, symmetric tied-gate DGMOSFET has the best power conversion efficiency and the lowest power consumption. Published version 2012-02-02T05:15:27Z 2019-12-06T18:50:29Z 2012-02-02T05:15:27Z 2019-12-06T18:50:29Z 2011 2011 Journal Article Vaddi, R., Agarwal, R. P., Dasgupta, S., & Kim, T. T. (2011). Design and Analysis of Double-Gate MOSFETs for Ultra-Low Power Radio Frequency Identification (RFID): Device and Circuit Co-Design. Journal of Low Power Electronics and Applications, 1(2), 277-302. 2079-9268(electronic) https://hdl.handle.net/10356/94092 http://hdl.handle.net/10220/7491 10.3390/jlpea1020277 163062 en Journal of low power electronics and applications © 2011 by the authors; licensee MDPI, Basel, Switzerland. 26 p. application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits Vaddi, Ramesh. Agarwal, Rajendra P. Dasgupta, Sudeb. Kim, Tony Tae-Hyoung Design and analysis of double-gate MOSFETs for ultra-low power radio frequency identification (RFID) : device and circuit co-design |
| title | Design and analysis of double-gate MOSFETs for ultra-low power radio frequency identification (RFID) : device and circuit co-design |
| title_full | Design and analysis of double-gate MOSFETs for ultra-low power radio frequency identification (RFID) : device and circuit co-design |
| title_fullStr | Design and analysis of double-gate MOSFETs for ultra-low power radio frequency identification (RFID) : device and circuit co-design |
| title_full_unstemmed | Design and analysis of double-gate MOSFETs for ultra-low power radio frequency identification (RFID) : device and circuit co-design |
| title_short | Design and analysis of double-gate MOSFETs for ultra-low power radio frequency identification (RFID) : device and circuit co-design |
| title_sort | design and analysis of double gate mosfets for ultra low power radio frequency identification rfid device and circuit co design |
| topic | DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits |
| url | https://hdl.handle.net/10356/94092 http://hdl.handle.net/10220/7491 |
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