A 0.8-μW window SAR ADC with offset cancellation for digital DC–DC converters
This letter presents the design of a window successive approximation (SAR) analog-to-digital converter (ADC) using an ultra-fast, offset-cancelled auto-zero comparator for digital DC–DC converters. It is designed in a standard CMOS 0.18 μm process. The ADC has a dynamic reference voltage range to re...
| Main Authors: | , , |
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| Other Authors: | |
| Format: | Journal Article |
| Language: | English |
| Published: |
2013
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| Online Access: | https://hdl.handle.net/10356/98426 http://hdl.handle.net/10220/12409 |
| _version_ | 1826116730568572928 |
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| author | Foong, Huey Chian Tan, Meng Tong Zheng, Yuanjin |
| author2 | School of Electrical and Electronic Engineering |
| author_facet | School of Electrical and Electronic Engineering Foong, Huey Chian Tan, Meng Tong Zheng, Yuanjin |
| author_sort | Foong, Huey Chian |
| collection | NTU |
| description | This letter presents the design of a window successive approximation (SAR) analog-to-digital converter (ADC) using an ultra-fast, offset-cancelled auto-zero comparator for digital DC–DC converters. It is designed in a standard CMOS 0.18 μm process. The ADC has a dynamic reference voltage range to reduce power consumption. The auto-zero scheme of the comparator is realized internally with a preamplifier stage and a latch stage. Post-layout simulation shows that the response time of the comparator from low-to-high and high-to-low is 3.78 ns and 2.47 ns, respectively. The resolution of the proposed window SAR ADC is 7.5 mV. The ADC is fabricated as part of a digital DC–DC converter integrated circuit and measurement results show that an average power consumption of 0.8 μW is achieved. The transient time of the DC–DC converter is within 150 ns for a load current change of 495 mA. |
| first_indexed | 2024-10-01T04:16:10Z |
| format | Journal Article |
| id | ntu-10356/98426 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T04:16:10Z |
| publishDate | 2013 |
| record_format | dspace |
| spelling | ntu-10356/984262020-03-07T14:00:30Z A 0.8-μW window SAR ADC with offset cancellation for digital DC–DC converters Foong, Huey Chian Tan, Meng Tong Zheng, Yuanjin School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering This letter presents the design of a window successive approximation (SAR) analog-to-digital converter (ADC) using an ultra-fast, offset-cancelled auto-zero comparator for digital DC–DC converters. It is designed in a standard CMOS 0.18 μm process. The ADC has a dynamic reference voltage range to reduce power consumption. The auto-zero scheme of the comparator is realized internally with a preamplifier stage and a latch stage. Post-layout simulation shows that the response time of the comparator from low-to-high and high-to-low is 3.78 ns and 2.47 ns, respectively. The resolution of the proposed window SAR ADC is 7.5 mV. The ADC is fabricated as part of a digital DC–DC converter integrated circuit and measurement results show that an average power consumption of 0.8 μW is achieved. The transient time of the DC–DC converter is within 150 ns for a load current change of 495 mA. 2013-07-26T07:11:44Z 2019-12-06T19:55:09Z 2013-07-26T07:11:44Z 2019-12-06T19:55:09Z 2011 2011 Journal Article Foong, H. C., Tan, M. T., & Zheng, Y. (2012). A 0.8-μW window SAR ADC with offset cancellation for digital DC–DC converters. Analog Integrated Circuits and Signal Processing, 70(1), 133-139. https://hdl.handle.net/10356/98426 http://hdl.handle.net/10220/12409 10.1007/s10470-011-9702-x en Analog integrated circuits and signal processing © 2011 Springer Science+Business Media, LLC. |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering Foong, Huey Chian Tan, Meng Tong Zheng, Yuanjin A 0.8-μW window SAR ADC with offset cancellation for digital DC–DC converters |
| title | A 0.8-μW window SAR ADC with offset cancellation for digital DC–DC converters |
| title_full | A 0.8-μW window SAR ADC with offset cancellation for digital DC–DC converters |
| title_fullStr | A 0.8-μW window SAR ADC with offset cancellation for digital DC–DC converters |
| title_full_unstemmed | A 0.8-μW window SAR ADC with offset cancellation for digital DC–DC converters |
| title_short | A 0.8-μW window SAR ADC with offset cancellation for digital DC–DC converters |
| title_sort | 0 8 μw window sar adc with offset cancellation for digital dc dc converters |
| topic | DRNTU::Engineering::Electrical and electronic engineering |
| url | https://hdl.handle.net/10356/98426 http://hdl.handle.net/10220/12409 |
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