Effect of direct current stressing to Cu–Cu bond interface imperfection for three dimensional integrated circuits
The ability to be used as both a glue layer and the interconnection line has put Cu metal interconnection as the ultimate goal for 3D-IC. However, the inherent properties of Cu–Cu bond interface that are not always perfect have raised some concerns. This work investigates the evolution of the Cu–Cu...
| Main Authors: | , , , , |
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| Other Authors: | |
| Format: | Journal Article |
| Language: | English |
| Published: |
2013
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/98611 http://hdl.handle.net/10220/9997 |
| _version_ | 1826118478342389760 |
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| author | Made, Riko I. Peng, Lan Li, Hong Yu Gan, Chee Lip Tan, Chuan Seng |
| author2 | School of Materials Science & Engineering |
| author_facet | School of Materials Science & Engineering Made, Riko I. Peng, Lan Li, Hong Yu Gan, Chee Lip Tan, Chuan Seng |
| author_sort | Made, Riko I. |
| collection | NTU |
| description | The ability to be used as both a glue layer and the interconnection line has put Cu metal interconnection as the ultimate goal for 3D-IC. However, the inherent properties of Cu–Cu bond interface that are not always perfect have raised some concerns. This work investigates the evolution of the Cu–Cu bond interface that had been subjected to prolonged electrical current stress. Interface evolutions were characterized by a combination of electrical current stressing and bond interface cross-sectional analysis. While interface improvement was observed in terms of interface void reduction after current stressing, early failures to the interconnection line adjacent to the bond interface were observed. Electromigration had driven void migration from the large bond interface area to the much smaller adjoining interconnect line. This potentially has a significant impact on the future of 3D-IC technology that utilizes Cu–Cu bonding. However, this problem can be mitigated by inserting a barrier layer in between the bond interface and the interconnect line to prevent the migration of the voids into the interconnect line |
| first_indexed | 2024-10-01T04:44:05Z |
| format | Journal Article |
| id | ntu-10356/98611 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T04:44:05Z |
| publishDate | 2013 |
| record_format | dspace |
| spelling | ntu-10356/986112020-06-01T10:01:52Z Effect of direct current stressing to Cu–Cu bond interface imperfection for three dimensional integrated circuits Made, Riko I. Peng, Lan Li, Hong Yu Gan, Chee Lip Tan, Chuan Seng School of Materials Science & Engineering School of Electrical and Electronic Engineering DRNTU::Engineering::Materials::Metallic materials::Alloys The ability to be used as both a glue layer and the interconnection line has put Cu metal interconnection as the ultimate goal for 3D-IC. However, the inherent properties of Cu–Cu bond interface that are not always perfect have raised some concerns. This work investigates the evolution of the Cu–Cu bond interface that had been subjected to prolonged electrical current stress. Interface evolutions were characterized by a combination of electrical current stressing and bond interface cross-sectional analysis. While interface improvement was observed in terms of interface void reduction after current stressing, early failures to the interconnection line adjacent to the bond interface were observed. Electromigration had driven void migration from the large bond interface area to the much smaller adjoining interconnect line. This potentially has a significant impact on the future of 3D-IC technology that utilizes Cu–Cu bonding. However, this problem can be mitigated by inserting a barrier layer in between the bond interface and the interconnect line to prevent the migration of the voids into the interconnect line Accepted Version 2013-05-27T06:49:18Z 2019-12-06T19:57:33Z 2013-05-27T06:49:18Z 2019-12-06T19:57:33Z 2013 2013 Journal Article Made, R. I., Lan, P., Li, H. Y., Gan, C. L., & Tan, C. S. (2013). Effect of direct current stressing to Cu–Cu bond interface imperfection for three dimensional integrated circuits. Microelectronic Engineering, 106, 149-154. https://hdl.handle.net/10356/98611 http://hdl.handle.net/10220/9997 10.1016/j.mee.2013.01.020 172744 en Microelectronic engineering © 2013 Elsevier B.V. This is the author created version of a work that has been peer reviewed and accepted for publication by Microelectronic Engineering, Elsevier B.V. It incorporates referee’s comments but changes resulting from the publishing process, such as copyediting, structural formatting, may not be reflected in this document. The published version is available at: [http://dx.doi.org.ezlibproxy1.ntu.edu.sg/10.1016/j.mee.2013.01.020]. application/pdf |
| spellingShingle | DRNTU::Engineering::Materials::Metallic materials::Alloys Made, Riko I. Peng, Lan Li, Hong Yu Gan, Chee Lip Tan, Chuan Seng Effect of direct current stressing to Cu–Cu bond interface imperfection for three dimensional integrated circuits |
| title | Effect of direct current stressing to Cu–Cu bond interface imperfection for three dimensional integrated circuits |
| title_full | Effect of direct current stressing to Cu–Cu bond interface imperfection for three dimensional integrated circuits |
| title_fullStr | Effect of direct current stressing to Cu–Cu bond interface imperfection for three dimensional integrated circuits |
| title_full_unstemmed | Effect of direct current stressing to Cu–Cu bond interface imperfection for three dimensional integrated circuits |
| title_short | Effect of direct current stressing to Cu–Cu bond interface imperfection for three dimensional integrated circuits |
| title_sort | effect of direct current stressing to cu cu bond interface imperfection for three dimensional integrated circuits |
| topic | DRNTU::Engineering::Materials::Metallic materials::Alloys |
| url | https://hdl.handle.net/10356/98611 http://hdl.handle.net/10220/9997 |
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