Fast simulation of hybrid CMOS and STT-MTJ circuits with identified internal state variables
Hybrid integration of CMOS and non-volatile memory (NVM) devices has become the technology foundation for emerging non-volatile memory based computing. The primary challenge to validate a hybrid system with both CMOS and non-volatile devices is to develop a SPICE-like simulator that can simulate the...
| Main Authors: | , , |
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| Format: | Conference Paper |
| Language: | English |
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2013
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| Online Access: | https://hdl.handle.net/10356/98706 http://hdl.handle.net/10220/12534 |
| _version_ | 1826112972759498752 |
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| author | Shang, Yang Fei, Wei Yu, Hao |
| author2 | School of Electrical and Electronic Engineering |
| author_facet | School of Electrical and Electronic Engineering Shang, Yang Fei, Wei Yu, Hao |
| author_sort | Shang, Yang |
| collection | NTU |
| description | Hybrid integration of CMOS and non-volatile memory (NVM) devices has become the technology foundation for emerging non-volatile memory based computing. The primary challenge to validate a hybrid system with both CMOS and non-volatile devices is to develop a SPICE-like simulator that can simulate the dynamic behavior of hybrid system accurately and efficiently. Since spin-transfer-toque magnetic-tunneling-junction (STT-MTJ) device is one of the most promising candidates of next generation NVM devices, it is under great interest in including this new device in the standard CMOS design flow. The previous approaches require complex equivalent circuits to represent the STT-MTJ device, and ignore dynamic effect without consideration of internal states. This paper proposes a new modified nodal analysis for STT-MTJ device with identified internal state variables. As demonstrated by a number of experiment examples on hybrid systems with both CMOS and STT-MTJ devices, our newly developed SPICE-like simulator can deal with the dynamic behavior of STT-MTJ device under arbitrary driving condition and reduce the CPU time by more than 20 times for memory circuits when compared to the previous equivalent circuit approaches. |
| first_indexed | 2024-10-01T03:15:54Z |
| format | Conference Paper |
| id | ntu-10356/98706 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T03:15:54Z |
| publishDate | 2013 |
| record_format | dspace |
| spelling | ntu-10356/987062020-03-07T13:24:48Z Fast simulation of hybrid CMOS and STT-MTJ circuits with identified internal state variables Shang, Yang Fei, Wei Yu, Hao School of Electrical and Electronic Engineering Asia and South Pacific Design Automation Conference (17th : 2012 : Sydney, NSW) DRNTU::Engineering::Electrical and electronic engineering Hybrid integration of CMOS and non-volatile memory (NVM) devices has become the technology foundation for emerging non-volatile memory based computing. The primary challenge to validate a hybrid system with both CMOS and non-volatile devices is to develop a SPICE-like simulator that can simulate the dynamic behavior of hybrid system accurately and efficiently. Since spin-transfer-toque magnetic-tunneling-junction (STT-MTJ) device is one of the most promising candidates of next generation NVM devices, it is under great interest in including this new device in the standard CMOS design flow. The previous approaches require complex equivalent circuits to represent the STT-MTJ device, and ignore dynamic effect without consideration of internal states. This paper proposes a new modified nodal analysis for STT-MTJ device with identified internal state variables. As demonstrated by a number of experiment examples on hybrid systems with both CMOS and STT-MTJ devices, our newly developed SPICE-like simulator can deal with the dynamic behavior of STT-MTJ device under arbitrary driving condition and reduce the CPU time by more than 20 times for memory circuits when compared to the previous equivalent circuit approaches. 2013-07-31T02:31:22Z 2019-12-06T19:58:41Z 2013-07-31T02:31:22Z 2019-12-06T19:58:41Z 2012 2012 Conference Paper https://hdl.handle.net/10356/98706 http://hdl.handle.net/10220/12534 10.1109/ASPDAC.2012.6165009 en |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering Shang, Yang Fei, Wei Yu, Hao Fast simulation of hybrid CMOS and STT-MTJ circuits with identified internal state variables |
| title | Fast simulation of hybrid CMOS and STT-MTJ circuits with identified internal state variables |
| title_full | Fast simulation of hybrid CMOS and STT-MTJ circuits with identified internal state variables |
| title_fullStr | Fast simulation of hybrid CMOS and STT-MTJ circuits with identified internal state variables |
| title_full_unstemmed | Fast simulation of hybrid CMOS and STT-MTJ circuits with identified internal state variables |
| title_short | Fast simulation of hybrid CMOS and STT-MTJ circuits with identified internal state variables |
| title_sort | fast simulation of hybrid cmos and stt mtj circuits with identified internal state variables |
| topic | DRNTU::Engineering::Electrical and electronic engineering |
| url | https://hdl.handle.net/10356/98706 http://hdl.handle.net/10220/12534 |
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